Parallel Transistor Layout for Uniform Power Loop Inductance
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Solution Overview
Problem
Existing semiconductor devices with multiple transistors connected in parallel face instability due to variations in inductance within the power loop, affecting their operational stability.
Innovation Solution
The semiconductor device design includes transistors and diodes connected in parallel, with specific conductive patterns and connection members that reduce the inductance variation between transistors, ensuring stable operations by direct connections and independent connection members.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple transistors are connected in parallel to increase current capacity, then the power handling capability is improved, but inductance variation within the power loop increases causing operational instability
Solution Approach 1:
The power loop is segmented into multiple independent paths, each with its own connection members. This segmentation ensures that each transistor has a dedicated low-inductance path to the conductive patterns, reducing the overall inductance variation when multiple transistors are connected in parallel.
Solution Approach 2:
Different regions of the device are assigned different functions: transistors are arranged in a first region with their source/emitter electrodes connected to a first conductive pattern, while diodes are arranged in a second region with their anode electrodes connected to a second conductive pattern. This local quality assignment optimizes the inductance characteristics for each functional group.
2Area of stationary object
If transistors are arranged adjacent to each other to reduce device area, then the area is reduced, but inductance variation within the power loop increases
Solution Approach 1:
The connection structure extends into the vertical dimension with conductive patterns arranged at different levels. The first conductive pattern is electrically connected to the second conductive pattern through vertical interconnections, creating a three-dimensional power distribution network that reduces inductance variation while maintaining compact horizontal footprint.
Data Source
AI summary
A semiconductor device includes a plurality of transistors electrically connected to each other in parallel, the plurality of transistors respectively including first electrodes, a diode electrically connected in parallel to the plurality of transistors, the diode including an anode electrode, a first conductive pattern, a second conductive pattern electrically connected to the first conductive pattern, a plurality of first connection members directly connecting the first electrodes of the plurality of transistors to the first conductive pattern, respectively, and a second connection member connecting the anode electrode to the second conductive pattern. Each of the first electrodes is a source electrode or an emitter electrode. The plurality of transistors are arranged adjacent to each other.