Parallel Transistor Memory Circuit for Low Resistance
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Solution Overview
Problem
As semiconductor memory cells become smaller and more complex, the resistance of conductive lines within these devices affects their performance, leading to challenges in achieving optimal read and write currents, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of a memory circuit design where transistors are configured in parallel to share word lines, reducing equivalent resistance and enhancing read and write currents by coupling first and second transistors in parallel with each other, thereby improving memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are made smaller and more complex, then storage capacity increases, but conductive line resistance increases affecting performance
Solution Approach 1:
The patent merges multiple transistors in parallel configurations to share common word lines and bit lines. Specifically, multiple program transistors share a program word line, and multiple read transistors share a read word line. This merging approach reduces the number of independent conductive lines needed, thereby reducing overall resistance and improving signal integrity while maintaining high storage capacity.
2Reliability
If transistors are configured in parallel to share word lines, then equivalent resistance decreases and read/write currents increase, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing transistors that can serve multiple purposes. The same transistor structure and layout are reused across different memory cells sharing common word lines and bit lines. This universal design approach reduces the need for unique conductive lines for each cell, thereby reducing resistance and improving current flow while the modular nature of the design actually simplifies overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in increased read and write currents, leading to improved reading and writing performance compared to other approaches, making the memory circuit more efficient and effective.
Implementation Method 1
the resistance of conductive lines within these devices are also changed affecting the characteristics of these devices and overall memory cell performance
Data Source
AI summary
A memory circuit array includes a first read device and a first program device. The first read device is coupled to a first bit line. The first read device includes a first transistor coupled to a first word line, and a second transistor coupled to the first word line. The first program device is coupled to the first read device. The first program device includes a third transistor coupled to a second word line, and a fourth transistor coupled to the second word line.