Parallel Power Transistor Circuit for Low-Current Probe Testing
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Solution Overview
Problem
Existing electronic circuits with power transistors face challenges in efficiently testing the integrity of the circuits, particularly during manufacturing, due to the high currents required and the limitations of testing under tips.
Innovation Solution
The proposed circuit design includes a plurality of elementary transistors connected in parallel, with specific switch configurations to ensure identical control voltages across all transistors, allowing for testing under tips and reducing current consumption during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high current is used for testing power transistors, then testing completeness is improved, but current consumption increases and testing under tips becomes difficult
Solution Approach 1:
The power transistor is divided into multiple elementary transistors connected in parallel. During testing, only a first set of these elementary transistors is activated through selective switching, allowing comprehensive testing of the power transistor's functionality while limiting the total current to manageable levels. This segmentation enables reliable testing without requiring excessive current that would be difficult to manage under tip conditions.
2Ease of operation
If multiple sets of elementary transistors are connected in parallel, then current distribution control is improved, but circuit complexity increases
Solution Approach 1:
Switches are introduced as intermediary elements between the control node and each set of elementary transistors. These switches act as mediators that selectively connect or disconnect specific sets of elementary transistors from the control node, enabling precise control over current distribution among parallel transistor sets. This intermediary switching mechanism provides excellent current control while adding only moderate circuit complexity through the use of standard switching components.
Data Source
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AI summary
The present description relates to a circuit (100) comprising a plurality of elementary transistors connected in parallel between a node of application of a first potential of a supply voltage and a load (104), the plurality of transistors comprising a first set (114) of elementary transistors whose gates are coupled to a control node (127) by a first circuit (128), and at least a second set (110, 112) of elementary transistors whose gates are coupled to the control node (127) by a second circuit (132), the second circuit having two states, the first and second circuits being adapted to provide a control voltage substantially identical to the gates of the first and second sets of elementary transistors when the second circuit is in one of the two states.