Parallel Transistor Resistance Switching Memory Cell
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Solution Overview
Problem
The electronic memory device industry faces challenges in increasing data storage capacity while maintaining or reducing device size and cost, as well as improving performance, with traditional approaches like reducing memory cell size becoming costly due to rising process costs.
Innovation Solution
The integration of transistors and resistance switching devices in parallel within memory cells, allowing each to independently store data, with transistors configured to switch between threshold voltages and resistance switching devices configured to switch between resistances, enabling higher bit density and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase bit density, then data storage capacity per unit area increases, but manufacturing process cost increases more rapidly than the memory-cell-reduction rate
Solution Approach 1:
The patent combines a transistor and a resistance switching device into a single memory cell structure, where the transistor provides storage capability and the resistance switching device provides readout functionality. This merging allows the memory cell to achieve higher bit density without proportionally increasing manufacturing complexity, as the resistance switching device can be integrated alongside the transistor using complementary processes.
Solution Approach 2:
The transistor serves multiple functions: it stores data through threshold voltage changes and also acts as a switch to control current flow during readout operations. The resistance switching device provides both storage and readout functions. This multi-functionality reduces the need for separate dedicated components, thereby reducing manufacturing cost while increasing storage capacity.
2Reliability
If transistor and resistance switching device are connected in series, then current flow is controlled, but readout accuracy is reduced due to threshold voltage variations
Solution Approach 1:
The patent segments the memory cell into two independent functional components: a transistor for data storage and a resistance switching device for readout. By connecting them in parallel rather than series, the readout function is separated from the storage function, allowing independent optimization of each component's performance and eliminating the readout accuracy problems caused by threshold voltage variations in series configurations.
Solution Approach 2:
The resistance switching device acts as an intermediary between the transistor and the readout circuitry. It converts the transistor's threshold voltage state into a resistance state that can be reliably measured, providing a mediator that translates the storage state into a readable signal without being directly affected by threshold voltage variations.
3Ease of manufacture
If traditional memory cell structures are used, then manufacturing process is simple, but bit density cannot be sufficiently increased
Solution Approach 1:
The patent embeds the resistance switching device within or alongside the transistor structure, creating a nested configuration where the two devices share common manufacturing steps and packaging. This nesting approach allows the memory cell to achieve higher bit density by utilizing the space-efficient parallel connection while maintaining manufacturing simplicity through shared fabrication processes.
Data Source
AI summary
A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.