Parallel High-Frequency Transistor Layout for Uniform Thermal Bias
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Solution Overview
Problem
Existing high frequency transistors face challenges in maintaining uniform temperature distribution among parallel-connected unit transistors, leading to nonuniform operation and performance deterioration, while existing solutions like thermistors and bias circuits increase costs and substrate area.
Innovation Solution
A high frequency transistor design with pads and conductors on a silicon substrate connected to unit transistors, where the conductors' ends are separated and electrically connected via the heated silicon substrate, reducing the resistance value of the stabilization circuit and promoting uniform temperature distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple unit transistors are connected in parallel to increase power output, then the saturated output power increases, but nonuniform temperature distribution occurs causing deterioration in power added efficiency
Solution Approach 1:
The patent applies local quality by providing stabilization circuits with different resistance values to different unit transistors based on their position. Specifically, the center unit transistor (which generates more heat) is equipped with a stabilization circuit having a smaller resistance value compared to the end unit transistors. This local differentiation compensates for the nonuniform temperature distribution, ensuring that each transistor operates efficiently and maintaining overall power added efficiency while achieving high saturated output power through parallel connection.
2Reliability
If a stabilization circuit with resistor and capacitor is connected to suppress oscillation, then oscillation is suppressed, but the gain of the high frequency transistor is reduced
Solution Approach 1:
The patent applies parameter changes by optimizing the resistance values of the stabilization circuits for different unit transistors. By setting smaller resistance values for center transistors and larger resistance values for end transistors, the patent achieves effective oscillation suppression while minimizing the impact on gain. This parameter optimization allows the stabilization circuit to suppress oscillation without excessively reducing the overall gain of the high frequency transistor.
3Temperature
If the resistance value of stabilization circuit is reduced to suppress heat generation in center transistor, then temperature uniformity improves, but the attenuation of high frequency signal increases
Solution Approach 1:
The patent applies local quality by implementing different resistance values in stabilization circuits for different positions of unit transistors. The center unit transistor, which experiences higher temperature, is equipped with a stabilization circuit having a smaller resistance value to suppress heat generation and improve temperature uniformity. The end unit transistors have stabilization circuits with larger resistance values to minimize signal attenuation. This localized differentiation resolves the contradiction between temperature uniformity and signal attenuation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves transistor performance by suppressing nonuniformity in temperature, enhancing power added efficiency without significantly increasing costs or substrate area, and allowing flexible bias circuit configurations.
Implementation Method 1
the other end of the first conductor and the other end of the second conductor are electrically connected to each other via the silicon substrate heated by heat from the corresponding unit transistor
Data Source
AI summary
Unit transistors are provided on a semiconductor substrate and connected in parallel to one another. Capacitors are respectively connected to gate electrodes of the unit transistors. Resistors are respectively connected to the capacitors in parallel. First and second pads are provided on an upper surface of the semiconductor substrate and respectively connected to one end and the other end of the resistor connected to at least the unit transistor in the center among the unit transistors arranged in a row. First and second conductors are provided on a silicon substrate arranged above the semiconductor substrate. A first bump connects the first pad and one end of the first conductor. A second bump connects the second pad and one end of the second conductor. The other ends of the first and second conductors are set in contact with the silicon substrate and are separated from and face each other.