Parallel Turbo Decoder Architecture for Low-Latency Trellis Processing
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Solution Overview
Problem
Conventional turbo decoders, such as those using the Log-BCJR algorithm, are limited by their serial nature and data dependencies, resulting in low processing throughputs and high latencies, which are inadequate for next-generation wireless communication standards requiring multi-gigabit throughputs and ultra-low end-to-end latencies.
Innovation Solution
A fully parallel turbo detection processor is introduced, where processing elements associated with trellis stages operate autonomously and in parallel, combining a priori forward, backward state metrics, and soft decision values to generate extrinsic metrics, allowing simultaneous processing of all turbo-encoded bits and reducing data dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Log-BCJR algorithm is used for iterative decoding of turbo codes, then decoding accuracy is improved, but processing throughput is limited and latency is high due to serial processing
Solution Approach 1:
The decoding process is segmented into independent processing elements, each handling specific trellis stages. These segments can operate in parallel without data dependencies, transforming the serial Log-BCJR algorithm into a parallel architecture that maintains decoding accuracy while dramatically improving throughput
Solution Approach 2:
The algorithm transitions from temporal serial processing to spatial parallel processing by distributing processing elements across multiple dimensions. Each processing element operates simultaneously on different trellis stages, converting time-based sequential execution into space-based parallel execution
2Reliability
If the Log-BCJR algorithm is used for iterative decoding, then error correction capability is enhanced, but end-to-end latency increases due to multiple time periods required for processing
Solution Approach 1:
The decoding latency is reduced by segmenting the processing into independent parallel elements that operate simultaneously. Each processing element completes its computation in a single clock cycle, eliminating the multiple sequential time periods required by the traditional Log-BCJR algorithm
Solution Approach 2:
The parallel architecture enables continuous processing without idle waiting periods. All processing elements operate continuously and simultaneously throughout the decoding process, eliminating the temporal gaps and sequential dependencies that cause latency in serial processing
3Productivity
If fully parallel processing is implemented for turbo decoding, then processing throughput is improved, but data dependencies between forward and backward recursions must be resolved
Solution Approach 1:
The data dependencies between forward and backward recursions are extracted and eliminated by designing processing elements that operate independently. Each processing element contains all necessary computations to produce extrinsic information without requiring intermediate results from neighboring elements, removing the dependency chain
Solution Approach 2:
Extrinsic information serves as an intermediary that enables parallel processing. Each processing element generates extrinsic information based on its local inputs, and this extrinsic information is then made available to all other processing elements simultaneously, mediating the communication without creating sequential dependencies
Data Source
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Figure 4(a)
AI summary
A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.