Parallel Turbo Decoder Windows to Avoid Interleaving Contention
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Solution Overview
Problem
Current turbo decoders, particularly those using the Log-BCJR algorithm, have limited processing throughput and high processing latency due to their serial nature, which restricts the achievable transmission throughput and end-to-end latency in wireless communication systems, especially for next-generation standards.
Innovation Solution
A turbo decoder circuit with a configurable network that allows for arbitrarily parallel processing, enabling each processing element to perform calculations across multiple trellis stages independently, and a predetermined schedule to manage the interleaving and delivery of soft decision values, avoiding contention and allowing dynamic configuration of window sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Log-BCJR algorithm is used for iterative decoding of turbo codes, then decoding accuracy is improved, but processing throughput is limited and processing latency increases due to the inherently serial nature of the algorithm
Solution Approach 1:
The patent divides the trellis into multiple windows of trellis stages, with each processing element responsible for a specific window. This segmentation allows parallel processing of different windows simultaneously, breaking the serial bottleneck while maintaining the iterative decoding accuracy of the Log-BCJR algorithm through coordinated information exchange between processing elements.
Solution Approach 2:
The patent introduces a spatial dimension for parallelism by distributing processing elements across multiple windows of the trellis. Instead of processing sequentially in time, multiple processing elements operate simultaneously on different windows, effectively adding a parallel processing dimension that increases throughput without compromising decoding accuracy.
2Reliability
If the Log-BCJR algorithm is applied alternately to two convolutional codes with numerous consecutive time periods, then iterative decoding is achieved, but processing latency increases
Solution Approach 1:
The patent segments the iterative decoding process by assigning different processing elements to handle different windows during the same clock cycle. This allows multiple stages of iterative decoding to progress simultaneously across different windows, reducing the total time required while maintaining the alternating application to upper and lower convolutional codes.
Solution Approach 2:
The patent enables continuous useful action by ensuring that processing elements operate every clock cycle on their assigned windows without idle periods. The predetermined schedule and configurable network ensure continuous flow of soft decision values between processing elements, eliminating wait states and reducing overall processing latency.
3Productivity
If a fully-parallel architecture is implemented for turbo decoding, then processing throughput increases, but device complexity and hardware resources increase
Solution Approach 1:
The patent segments the parallel processing architecture into multiple processing elements that share common resources such as the configurable network and memory structures. Each processing element handles a specific window but shares the interleaving/deinterleaving infrastructure, reducing overall hardware complexity compared to completely independent parallel processors while maintaining high throughput.
Solution Approach 2:
The configurable network serves multiple functions: it acts as an interleaver for soft decision values between processing elements, a deinterleaver for received values, and a routing structure for information exchange. This multi-functionality reduces the need for separate dedicated hardware for each operation, lowering device complexity while supporting parallel processing.
4Ease of manufacture
If fixed window sizes are used for parallel processing elements, then hardware implementation is simplified, but adaptability to different frame sizes is reduced
Solution Approach 1:
The patent implements dynamic window sizing where the number of windows and their sizes can be configured based on the frame size being decoded. The configurable network adapts its interconnection pattern according to the active processing elements and window configuration, allowing the same hardware to efficiently handle different frame sizes without fixed constraints while maintaining implementation feasibility.
Data Source
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AI summary
A turbo decoder circuit performs a turbo decoding process to recover a frame of data symbols from a received signal comprising soft decision values for each data symbol of the frame. The data symbols of the frame have been encoded with a turbo encoder comprising upper and lower convolutional encoders which can each be represented by a trellis, and an interleaver which interleaves the encoded data between the upper and lower convolutional encoders. The turbo decoder circuit comprises a clock, a configurable network circuitry for interleaving soft decision values, an upper decoder and a lower decoder. Each of the upper and lower decoders include processing elements, which are configured, during a series of consecutive clock cycles, iteratively to receive, from the configurable network circuitry, a priori soft decision values pertaining to data symbols associated with a window of an integer number of consecutive trellis stages representing possible paths between states of the upper or lower convolutional encoder. The processing elements perform parallel calculations associated with the window using the a priori soft decision values in order to generate corresponding extrinsic soft decision values pertaining to the data symbols. The configurable network circuitry includes network controller circuitry which controls a configuration of the configurable network circuitry iteratively, during the consecutive clock cycles, to provide the a priori soft decision values for the upper decoder by interleaving the extrinsic soft decision values provided by the lower decoder, and to provide the a priori soft decision values for the lower decoder by interleaving the extrinsic soft decision values provided by the upper decoder. The interleaving performed by the configurable network circuitry controlled by the network controller is in accordance with a predetermined schedule, which provides the a priori soft decision values at different cycles of the one or more consecutive clock cycles to avoid contention between different a priori soft decision values being provided to the same processing element of the upper or the lower decoder during the same clock cycle. Accordingly the processing elements can have a window size which includes a number of stages of the trellis so that the decoder can be configured with an arbitrary number of processing elements, making the decoder circuit an arbitrarily parallel turbo decoder.