Parallel Verify Processing in Semiconductor Storage Devices
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Solution Overview
Problem
The increasing memory capacity of semiconductor storage devices leads to prolonged verify processing times due to the serial nature of verify processing in existing technologies, where each memory block is processed sequentially using a single verify amplifier.
Innovation Solution
The semiconductor storage device employs multiple sense amplifiers to perform verify processing in parallel, allowing simultaneous verification of multiple memory blocks by distributing the verify circuits across each sense amplifier block, thereby reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If verify processing is performed sequentially using one verify amplifier, then device complexity is reduced, but productivity deteriorates due to prolonged verify processing time
Solution Approach 1:
The verify amplifier is divided into multiple verify circuits, with each verify circuit assigned to a specific sense amplifier block. This segmentation allows parallel verification of multiple memory blocks simultaneously, improving verify processing speed while distributing the complexity across modular units rather than concentrating it in a single centralized verify amplifier.
2Quantity of substance
If memory capacity is increased, then storage capability is improved, but verify processing time increases due to serial processing
Solution Approach 1:
The memory array is divided into multiple memory blocks, each associated with a specific sense amplifier block and verify circuit. This segmentation enables parallel verification operations across multiple blocks simultaneously, allowing verify processing time to scale more efficiently with increased memory capacity rather than increasing linearly with total capacity.
Solution Approach 2:
The invention transitions from one-dimensional sequential verification (one block at a time) to two-dimensional parallel verification (multiple blocks simultaneously across different sense amplifier blocks). This dimensional change in processing architecture allows verify processing time to remain relatively constant even as memory capacity increases, since multiple verification operations proceed concurrently.
Data Source
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AI summary
To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.