Parallel Via Mesh Creation for Faster IC Layout Processing
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Solution Overview
Problem
The iterative and sequential process of creating via meshes in integrated circuits is time-consuming and resource-intensive, requiring significant computational power and designer expertise due to the complexity and precision needed at each stage, which affects the efficiency and scalability of integrated circuit design.
Innovation Solution
A parallel processing method is introduced where via mesh creation jobs are partitioned into sets based on proximity within the integrated circuit, assigned to different processing units, and processed simultaneously to reduce computation time and optimize design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If via meshes are created using sequential processing, then design precision and control are maintained, but computation time and resource consumption increase significantly
Solution Approach 1:
The patent divides the via mesh creation process into multiple independent tasks or regions, each handled by a separate processing unit. This segmentation allows parallel execution of via mesh creation operations, reducing total computation time while maintaining precision through localized control of each segment.
Solution Approach 2:
The patent introduces a parallel processing dimension to the traditionally sequential via mesh creation process. By utilizing multiple processing units that operate simultaneously on different portions of the circuit, the system adds a temporal and computational dimension, reducing overall execution time without compromising design precision.
2Reliability
If via mesh creation is performed iteratively, then design optimization is improved, but computational resource consumption and processing time increase
Solution Approach 1:
The patent segments the iterative optimization process into parallel tasks that can be executed simultaneously across multiple processing units. Each processing unit works on a specific portion of the circuit, allowing iterative optimizations to be performed in parallel rather than sequentially, reducing total computational resource consumption.
Solution Approach 2:
The patent maintains continuous iterative optimization by distributing it across multiple processing units that operate simultaneously. Rather than completing one iterative cycle sequentially before moving to the next, the system performs multiple iterative actions in parallel, maintaining continuous progress and reducing total computation time.
3Productivity
If more processing units are used for parallel via mesh creation, then computation time is reduced, but system complexity increases
Solution Approach 1:
The patent implements a segmentation strategy that divides the via mesh creation workload into manageable tasks suitable for distribution across multiple processing units. This segmentation enables parallel processing and improved productivity while keeping individual task complexity low, making the overall system more manageable.
Solution Approach 2:
The patent employs a universal processing framework that can handle multiple via mesh creation tasks across different processing units using common algorithms and data structures. This multi-functionality approach allows the system to scale productivity by adding processing units without proportionally increasing operational complexity, as the same standardized processes apply to all units.
Data Source
AI summary
Aspects of the invention include parallel creation of via meshes in an integrated circuit. Aspects include obtaining a plurality of via mesh creation jobs for an integrated circuit, obtaining existing wires and design rules for the integrated circuit, and partitioning the plurality of via mesh creation jobs into a plurality of sets of jobs, wherein the jobs in each set have a proximity to at least one another job in the set that is less than a threshold distance. Aspects also include assigning each of the plurality of sets of jobs to different processing units and creating, by each of the different processing units, a via mesh for each of the jobs in the assigned set of jobs.