Parallel Multi-Processor Video Codec for Sub-Frame Latency
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Solution Overview
Problem
Current video encoder-decoder systems face challenges in achieving low latency while maintaining high compression efficiency, particularly in achieving sub-frame latency with combined intra- and inter-frame prediction, and efficient parallel processing.
Innovation Solution
A parallel multi-processor system is employed to divide video frames into subsets allocated to respective processors for independent encoding and decoding, allowing for concurrent processing and interleaving of outputs across processors to reduce latency and buffer size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If video frames are processed sequentially by a single encoder-decoder system, then processing is simpler to implement, but latency increases and throughput decreases
Solution Approach 1:
The patent divides video frames into multiple subsets (e.g., tiles or slices) and assigns each subset to a separate processor in the parallel multi-processor system. This segmentation enables concurrent processing of different frame portions, reducing end-to-end latency while distributing the processing load across multiple independent units, thus managing system complexity through modular organization.
Solution Approach 2:
The patent introduces parallelism as an additional processing dimension by employing multiple processors that operate simultaneously on different frame subsets. This transforms the single-threaded sequential processing model into a multi-threaded parallel model, achieving sub-frame latency by processing multiple regions of a frame concurrently rather than sequentially.
2Productivity
If combined intra- and inter-frame prediction is used, then compression efficiency improves, but processing complexity and latency increase
Solution Approach 1:
The patent segments the frame into multiple independently processable subsets that can be encoded using combined intra- and inter-frame prediction techniques. Each processor handles its assigned subset with full prediction capabilities, enabling compression efficiency improvements while distributing the computational complexity across parallel processing units rather than concentrating it in a single processor.
3Reliability
If larger buffers are used to store encoded data, then data transmission reliability improves, but latency increases
Solution Approach 1:
The patent segments the encoded data stream into smaller units corresponding to different frame subsets processed by individual processors. This segmentation allows for smaller, more manageable buffers for each processor while maintaining overall data transmission reliability through parallel redundancy. The interleaved output from multiple processors reduces the impact of buffer latency on any single data stream.
Solution Approach 2:
The patent maintains continuous data flow from multiple parallel processors that independently encode and output their frame subsets. This continuous parallel production of encoded data ensures that transmission reliability is maintained through constant data availability while minimizing buffer latency, as each processor continuously feeds its subset without waiting for sequential processing completion.
Data Source
AI summary
Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.