Parallel Virtual Controller Simulation System
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Solution Overview
Problem
Current simulation systems for control systems in industrial processes are inefficient due to sequential execution of simulation steps, which limits their ability to simulate operations in real-time and hampers testing and validation processes.
Innovation Solution
Implementing a simulation system that executes simulation steps in parallel using multi-threaded and multi-core processors, allowing virtual controllers to complete previous steps and write results to shared memory before initiating subsequent steps, thereby improving processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If simulation steps are executed sequentially, then the simulation system maintains simplicity in control flow, but the simulation speed is limited and cannot keep up with real-time operations
Solution Approach 1:
The simulation system divides the control flow into discrete simulation steps that can be independently executed. Each virtual controller processes its own simulation step independently, allowing parallel execution while maintaining clear control boundaries. This segmentation enables the system to achieve real-time simulation speed without requiring complex inter-dependent control logic.
Solution Approach 2:
The patent transitions from sequential (one-dimensional) execution to parallel (multi-dimensional) execution by utilizing multi-core processors. Virtual controllers are distributed across multiple processing cores, executing simulation steps simultaneously in different dimensional spaces. This dimensional change allows the system to maintain simple control flow logic while achieving significant speedup through parallel processing.
2Productivity
If sequential execution is used, then memory access patterns are simple and predictable, but processor utilization is inefficient and simulation throughput is limited
Solution Approach 1:
The patent merges multiple virtual controller executions into a single parallel processing framework. Multiple virtual controllers are combined and executed simultaneously across available processor cores, maximizing processor utilization. The shared memory architecture allows these merged controllers to access common data structures efficiently, maintaining simple memory access patterns while achieving high throughput through combined execution.
3Loss of time
If parallel execution is implemented, then simulation speed increases significantly, but synchronization and memory management become more complex
Solution Approach 1:
The patent creates copies of simulation step execution logic for each virtual controller, allowing independent parallel execution without complex synchronization. Each virtual controller has its own instance of the simulation step routine, eliminating the need for intricate inter-controller synchronization mechanisms. This copying approach reduces synchronization complexity while maintaining parallel execution benefits.
Solution Approach 2:
The system uses lightweight, short-lived simulation step objects that are created and destroyed rapidly during parallel execution. These disposable simulation step instances minimize memory management complexity and reduce the need for complex synchronization protocols. By using cheap, short-lived objects instead of persistent complex data structures, the system achieves parallel execution with reduced synchronization overhead.
Data Source
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AI summary
A non-transitory tangible computer-readable medium may include instructions executable by a processor in a simulation system 30 to perform a simulation. The instructions may include to wait 58 for a plurality of virtual controllers 42 to complete a previous simulation step, write 60 a result of the previous simulation step from each of the plurality of virtual controllers 42 to a shared memory 50, read 64 an input from the memory 50 to each of the plurality of virtual controllers 42, initiate a simulation step on each of the plurality of virtual controllers 42, and upon initiation of the simulation step in each of the plurality of virtual controllers 42, indicate 74 completion of the simulation, in which the plurality of virtual controllers 42 include a controller model having a plurality of simulation steps and the instructions are configured to be executed by the processor in parallel.