Parallel Virtual I/O Mapping to Multiple Physical Adapters
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Solution Overview
Problem
Current data processing systems face inefficiencies in managing input/output (I/O) operations across multiple physical adapters, as they require serial mapping and unmapping of I/O buffer pages, leading to time-consuming processor cycles, especially when dealing with numerous adapters.
Innovation Solution
A method that maps virtual I/O requests to physical adapters in parallel by utilizing virtual and physical translation control entry (TCE) tables, allowing simultaneous mapping and execution of physical I/O requests across multiple adapters, thereby reducing the time-consuming serial process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If I/O buffer pages are mapped serially to multiple physical adapters, then mapping accuracy is ensured, but processing time increases significantly
Solution Approach 1:
The patent divides the I/O processing workflow into distinct segments: virtual I/O reception, physical adapter identification, parallel mapping execution, and result aggregation. Each segment is handled independently, allowing the mapping operation to be parallelized across multiple physical adapters without requiring sequential coordination, thus reducing processing time while managing complexity through structured division of labor
Solution Approach 2:
The system performs preliminary identification of all required physical adapters before executing the mapping operation. By determining the complete set of physical adapters needed upfront and preparing the mapping structure in advance, the system enables subsequent parallel mapping execution without requiring iterative coordination or repeated identification steps, thereby eliminating time losses associated with sequential processing
2Productivity
If serial mapping and unmapping of I/O buffer pages is performed, then mapping accuracy is maintained, but processor cycle efficiency deteriorates
Solution Approach 1:
The patent merges multiple sequential mapping operations into a single parallel mapping execution. Instead of mapping I/O buffer pages to each physical adapter one after another, the system combines all mapping operations into a unified parallel process that executes simultaneously across all identified physical adapters, dramatically improving processor cycle efficiency while maintaining mapping accuracy through consistent virtual-to-physical address translation
Solution Approach 2:
The system ensures continuous useful action by eliminating idle waiting periods between sequential mapping operations. All physical adapters receive their mappings simultaneously in a single continuous operation, keeping the processor continuously productive throughout the mapping phase without interruptions or waiting states that would occur in sequential execution, thereby maximizing processor cycle efficiency
3Productivity
If multiple physical adapters are used for virtual I/O, then I/O throughput increases, but mapping coordination overhead increases
Solution Approach 1:
The system performs preliminary identification of all physical adapters required for the virtual I/O operation before initiating the mapping process. By determining the complete set of physical adapters upfront and preparing the mapping structure in advance, the system enables subsequent parallel mapping execution without requiring iterative coordination or repeated identification steps, thereby eliminating time losses associated with sequential processing while maintaining the ability to utilize multiple adapters for high throughput
Solution Approach 2:
The patent segments the I/O processing workflow into distinct phases: virtual I/O reception, physical adapter identification, parallel mapping execution, and result aggregation. This segmentation allows the mapping operation to be parallelized across multiple physical adapters without requiring sequential coordination between them, thus enabling high I/O throughput while minimizing mapping coordination overhead through structured division of labor
Data Source
AI summary
Techniques are disclosed for performing input/output (I/O) requests to two or more physical adapters in parallel. An address for at least a first page associated with a virtual I/O request is mapped to an entry in a virtual translation control entry (TCE) table. A plurality of physical adapters required to service the virtual I/O request are identified. Upon determining, in each of the identified physical adapters, that an entry in the respective physical TCE table corresponding to the physical adapter is available, for each of the identified physical adapters, the entry in the virtual TCE table is mapped to an entry in the respective physical TCE table corresponding to the physical adapter, and a physical I/O request corresponding to each physical TCE table entry is issued to the respective physical adapter.