Parallel Circulation Viterbi Decoder for Faster Analog Decoding
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Solution Overview
Problem
Conventional Viterbi decoders require additional hardware and lengthen decoding time due to the need for memory storage and backtracking processes, while circulation type decoders suffer from reduced decoding speed as they start decoding operations sequentially after completing each bit.
Innovation Solution
A Viterbi decoder utilizing parallel circulation type decoding units with a control unit that designates processing parts and capacitors for parallel data processing, eliminating the need for separate memory storage and enabling simultaneous decoding operations across multiple units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Viterbi decoder uses memory storage and backtracking process, then decoding accuracy is maintained, but decoding time is lengthened and additional hardware is required
Solution Approach 1:
The decoder is divided into multiple independent decoding units (first decoding unit, second decoding unit, etc.), each capable of independently performing decoding operations. This segmentation allows parallel processing of different data bits, eliminating the sequential backtracking process while maintaining decoding accuracy through distributed computation across multiple units.
Solution Approach 2:
The invention transitions from sequential time-based processing to parallel spatial processing by adding multiple decoding units operating simultaneously. This dimensional change from single-thread sequential execution to multi-thread parallel execution eliminates the time penalty associated with backtracking while preserving decoding reliability.
2Device complexity
If circulation type decoder is used to eliminate memory hardware, then hardware complexity is reduced, but decoding speed decreases due to sequential operation
Solution Approach 1:
The circulation type decoder is segmented into multiple independent decoding units, each implementing the circulation logic locally without requiring centralized memory. This segmentation enables parallel operation of multiple units, simultaneously reducing hardware complexity (by eliminating memory) and increasing decoding speed (through parallel processing).
Solution Approach 2:
Multiple circulation type decoding units are merged into a parallel architecture where each unit independently processes different data bits. This combining approach maintains the hardware efficiency of circulation type decoders while achieving the speed improvement of parallel processing, as all units operate simultaneously without requiring memory storage.
3Productivity
If multiple decoding units operate in parallel, then decoding speed is improved, but control complexity increases
Solution Approach 1:
A control unit implements periodic action by sequentially enabling different decoding units at regular intervals synchronized with the input data stream. This periodic control pattern simplifies the coordination of parallel units, as each unit follows a predictable, repeating enable sequence rather than requiring complex dynamic control logic.
Solution Approach 2:
Each decoding unit is designed as a self-contained module that autonomously performs its decoding operations without requiring complex inter-unit coordination. The units self-service by independently processing their assigned data bits through the circulation logic, reducing the overall control complexity to simple enable signals from the control unit.
Data Source
AI summary
An analog Viterbi decoder for decoding an analog signal is provided that includes a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells arranged to correspond to respective nodes of a trellis diagram, for decoding analog input data using an analog signal processing cell having a circulation type connection structure in which the last processing part is connected to the first processing part; a control unit for performing in parallel a sequential designation of the processing parts with respect to the decoding units; an analog data storage unit including a plurality of capacitors connected in parallel with the processing parts provided in the decoding units; and a first switch unit for storing analog input data in a specific capacitor of the analog data storage units under the control of the control unit. Accordingly, the decoding speed can be remarkably improved.