Parallel Viterbi Decoder Using End-State Passing for High Data Rates
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Solution Overview
Problem
Current Viterbi decoders face challenges in handling high data rates due to inefficiencies and physical limitations of semiconductor technologies, leading to either excessive chip area consumption or elevated clock rates, making sequential decoders infeasible for modern standards like 10 GBASE-LRM.
Innovation Solution
The implementation of parallel Viterbi decoders that employ end-state information passing to increase efficiency, allowing for less area usage and higher data rate handling within a given heat budget, by using multiple decoders operating on overlapping data blocks with add-compare-select operations and eliminating the need for post-data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parallel Viterbi decoders are implemented to handle high data rates, then data rate capability is improved, but chip area consumption increases
Solution Approach 1:
The incoming data stream is divided into multiple blocks that are processed in parallel by multiple Viterbi decoders. Each decoder handles a specific block, allowing simultaneous processing and achieving high data rates while controlling the area required per decoder through efficient block management and overlap reduction.
Solution Approach 2:
End-state information from previously processed blocks is passed in advance to current block processing. This preliminary information allows decoders to start processing with optimized initial conditions, reducing the required post-data segment length and thereby reducing chip area while maintaining high data rate capability.
2Productivity
If parallel Viterbi decoders are implemented to handle high data rates, then processing speed is improved, but device complexity increases
Solution Approach 1:
The decoding task is segmented into multiple independent blocks processed by separate decoders, enabling parallel execution and improved processing speed. Each decoder maintains simplified logic for its specific block, reducing individual decoder complexity while achieving high overall productivity through parallelism.
Solution Approach 2:
End-state information is passed in advance to prepare decoders for upcoming blocks, eliminating the need for complex post-processing and reducing the required post-data segment. This preliminary action simplifies the decoder architecture while maintaining high processing speed.
3Reliability
If post-data segments are added to minimize block edge effects, then decoding accuracy is improved, but efficiency decreases
Solution Approach 1:
End-state information from previous blocks is passed in advance to current block processing, providing the necessary boundary conditions upfront. This eliminates or minimizes the need for post-data segments, maintaining decoding accuracy while significantly improving efficiency by allowing decoders to process complete data blocks without extended post-processing regions.
4Speed
If clock rates are elevated to handle high data rates in sequential decoders, then data rate capability is improved, but heat generation increases
Solution Approach 1:
The high data rate processing task is divided into multiple parallel decoders operating at lower, manageable clock rates. Each decoder handles a portion of the data stream simultaneously, achieving high overall data rate capability while keeping individual decoder clock rates and heat generation within acceptable limits.
Data Source
AI summary
A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.