Parallel Viterbi Butterfly Architecture for Low-Power Decoding
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Solution Overview
Problem
High-end processors are not suited for wireless applications due to power consumption and power handling requirements, and conventional microcontrollers are not efficient for Viterbi decoding due to slower operating frequencies and cost constraints.
Innovation Solution
A decoding system with a state metrics array, a butterfly unit, and a constraint length multiplexer is implemented, where the butterfly unit performs parallel operations using internal registers to reduce external memory access and power consumption, and the constraint length multiplexer generates new state metrics and transition bits efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-end processors are used for Viterbi decoding, then processing speed is improved, but power consumption increases
Solution Approach 1:
The Viterbi decoder is segmented into specialized functional units: butterfly units for parallel metric calculation, state metric arrays for storage, and trace-back units for path reconstruction. This segmentation allows each unit to be optimized for its specific function, achieving high processing speed while consuming less power than a general-purpose high-end processor.
Solution Approach 2:
The patent introduces intermediate state metric arrays and butterfly units as mediators between the received signal and the final decoded output. These intermediaries enable parallel processing of multiple state metrics simultaneously, improving processing speed while keeping each individual processing element simple and power-efficient.
2Use of energy by moving object
If conventional microcontrollers are used for Viterbi decoding, then power consumption is reduced, but processing speed decreases
Solution Approach 1:
The patent changes the architectural parameters of the microcontroller by introducing dedicated butterfly units that can perform multiple metric calculations in parallel, and state metric arrays that store intermediate results. This transforms a sequential microcontroller into a system capable of parallel processing, significantly improving processing speed while maintaining the low power consumption characteristics of microcontroller-based designs.
3Speed
If parallel butterfly operations are implemented, then processing speed is improved, but device complexity increases
Solution Approach 1:
The butterfly units are designed as universal processing elements that can handle multiple state metric calculations using the same hardware structure. Each butterfly unit can process different pairs of state metrics by changing the input connections, allowing parallel processing without proportionally increasing hardware complexity. The state metric arrays also serve multiple functions: storing current metrics, holding intermediate results, and providing inputs for trace-back operations.
Data Source
AI summary
A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.