Parallel Variable Length Code Encoding on VLIW Processors
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Solution Overview
Problem
Current variable length coding (VLC) methods are inefficient for Very Large Instruction Word (VLIW) architectures due to sequential operations, excessive conditional checks, and memory load delays, which limit parallelism and waste processing power.
Innovation Solution
The VLC process is parallelized by extending tables to encompass both level and run escape modes, reducing conditional checks and using a 64-element map to determine the full escape mode, allowing independent parallel paths for encoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential mode VLC encoding is used, then the encoding process is simple to implement, but processing speed and parallelism are limited
Solution Approach 1:
The patent segments the VLC encoding process into independent parallel paths by separating table mode encoding from escape mode encoding. Each path can be executed independently, allowing parallel processing on VLIW architectures. The segmentation eliminates sequential dependencies while maintaining encoding correctness through separate processing streams that converge only at the final bitstream output stage.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing model by introducing multiple independent encoding paths (table mode path, escape mode path). This dimensional change allows the encoder to exploit parallelism in the time dimension while maintaining the logical flow of encoding operations across different processing dimensions.
2Productivity
If multiple escape modes are explicitly coded, then encoding accuracy is maintained, but conditional checks and iteration length increase
Solution Approach 1:
The patent extracts the escape mode encoding logic from the main sequential flow and places it in a separate parallel path. By taking out the escape mode handling from the conditional sequence, the main encoding loop can proceed without excessive conditional checks. The escape mode path independently processes escape sequences and merges results, reducing iteration length in the critical encoding path.
Solution Approach 2:
The patent performs preliminary classification of run-level pairs to determine whether they require table mode or escape mode encoding before the main encoding loop. This preliminary action allows the encoder to set up parallel processing paths in advance, avoiding conditional checks during the critical encoding phase and reducing iteration length by pre-determining the encoding path for each coefficient.
3Power
If VLIW architecture parallelism is maximized, then processing power is utilized, but conditional registers are blocked for excessive cycles
Solution Approach 1:
The patent segments conditional checks into separate parallel paths, allowing conditional register usage to be distributed across independent processing streams rather than concentrated in a single sequential flow. This segmentation reduces the duration that conditional registers remain blocked, as each path can evaluate and clear its conditions independently, improving register availability for subsequent operations.
Data Source
AI summary
A novel algorithm is shown that allows efficient generation of Variable Length Codes using a Very Large Instruction Word processor with multiple execution units. The code generation is parallelized to take advantage of the multiple execution units, significantly reducing the cycle count and the execution time.