Parallel Voltage-to-Delay Converter Circuit for Linear High-Bandwidth ADCs
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Solution Overview
Problem
Existing voltage to delay (VTD) converters in analog to digital converters (ADCs) face challenges with signal integrity issues due to nonlinear responses, spurious free dynamic range (SDFR), and signal to noise ratio (SNR) degradation, particularly in current starved inverter and ramp and comparator architectures, leading to trade-offs between SNR and bandwidth.
Innovation Solution
A new VTD circuit architecture with multiple instances of a duplicated architecture, incorporating a kick signal to improve linearity and reduce effective capacitor requirements, while preventing inverter activation during the sampling period, thereby enhancing SNR, linearity, speed, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current starved inverter or ramp and comparator architectures are used in VTD converters, then bandwidth is improved, but signal integrity degrades due to nonlinear responses and SNR degradation
Solution Approach 1:
The VTD converter is divided into multiple identical sub-units (first VTD converter unit, second VTD converter unit, etc.) that operate in parallel. Each unit processes a portion of the conversion task, reducing the burden on individual units and improving overall signal integrity while maintaining high bandwidth through parallel operation.
Solution Approach 2:
Multiple copies of the VTD converter unit are created and operated simultaneously. The first VTD converter unit and second VTD converter unit are identical copies that process signals in parallel, providing redundant processing paths that improve signal integrity without sacrificing bandwidth.
2Reliability
If larger capacitors are used in VTD converters, then linearity and SNR are improved, but device area and complexity increase
Solution Approach 1:
The total capacitance requirement is segmented across multiple VTD converter units. Each unit uses a smaller capacitor (first capacitor in first unit, second capacitor in second unit, etc.), reducing individual component size and complexity while achieving the same overall linearity and SNR performance through parallel operation.
Solution Approach 2:
The design changes the operating parameters by using multiple units with smaller capacitors instead of a single unit with a large capacitor. This parameter transformation maintains the electrical performance (linearity and SNR) while reducing the physical size and complexity of individual components.
3Speed
If multiple VTD converter units operate in parallel, then bandwidth and speed are improved, but power consumption increases
Solution Approach 1:
The kick signal is applied periodically to charge the capacitors in each VTD converter unit at specific intervals. This periodic charging mechanism ensures that each unit operates efficiently only when needed, reducing unnecessary power consumption while maintaining high bandwidth through coordinated parallel operation.
Solution Approach 2:
Each VTD converter unit autonomously manages its own capacitor charging through the kick signal mechanism. The units self-regulate their power consumption by only actively charging capacitors when the kick signal is applied, rather than continuously consuming power, thus achieving high bandwidth with controlled power usage.
Data Source
AI summary
An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of O_RST signal.