Parallel Semiconductor Wafer Burn-In Testing via Multi-Probe Alignment
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Solution Overview
Problem
Conventional semiconductor wafer burn-in test equipment requires extensive time and significant facility investment due to the sequential testing of wafers and the need for complex equipment to apply voltage simultaneously to multiple wafers.
Innovation Solution
A semiconductor test equipment featuring a testing table with aligned contact units on a probe card, a holding tool, a voltage application circuit for parallel connection, and a characteristic measuring circuit to simultaneously apply voltage and measure semiconductor chip characteristics across multiple wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor wafers are tested sequentially by an automatic prober device, then the testing process is simple to implement, but the testing time becomes excessively long
Solution Approach 1:
The patent combines multiple contact units (each comprising a probe card and semiconductor wafer) into a single testing system. Multiple wafers are simultaneously contacted and tested in parallel on one testing table, merging what were previously separate sequential testing operations into a unified parallel testing process, thereby dramatically increasing throughput without requiring multiple independent prober devices
Solution Approach 2:
The patent transitions from one-dimensional sequential testing (one wafer at a time) to two-dimensional parallel testing by arranging multiple contact units side-by-side on the testing table. This spatial dimensionality change allows simultaneous voltage application and characteristic measurement across multiple wafers, effectively multiplying the testing capacity
2Productivity
If multiple automatic prober devices are introduced to simultaneously test multiple wafers, then the testing time is shortened, but the facility investment and equipment complexity increase significantly
Solution Approach 1:
The patent creates a universal testing platform where a single testing table can accommodate multiple contact units with different probe cards and wafer configurations. The voltage application circuit and characteristic measuring circuit serve multiple contact units simultaneously, making the system multi-functional and adaptable to various testing requirements without needing dedicated equipment for each wafer
Solution Approach 2:
The patent introduces a holding tool as an intermediary device that simultaneously holds multiple wafers and probe cards in their contacted states. This intermediary mechanism enables the coordination and stabilization of multiple contact units on the testing table, facilitating parallel testing while maintaining control and simplicity in the overall system architecture
Data Source
AI summary
A semiconductor test equipment can conduct a burn-in test, and has a testing table capable of aligning a plurality of contact units formed of a probe card having a plurality of contact probes each corresponding to each of a plurality of semiconductor chips formed on a semiconductor wafer to contact with the semiconductor wafer, and a holding tool for holding the semiconductor wafer and the probe card in a contacted state; a voltage application circuit having connection wiring lines provided in a manner capable of parallel connection of the plurality of contact units aligned on the testing table, and a plurality of connection units to apply a testing voltage to the semiconductor wafer held on each of the plurality of contact units; and a characteristic measuring circuit for measuring characteristics of the plurality of semiconductor chips formed on the semiconductor wafer according to application of the testing voltage.