Parallel Wires of Different Metal Materials via Double Patterning
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Solution Overview
Problem
As integrated circuit features are scaled down, electromigration becomes a significant concern due to increased power density, and refractory metals, while reducing electromigration, exhibit higher bulk resistivity, leading to increased interconnect delay and reliability issues.
Innovation Solution
The method involves forming parallel wires of different metal materials in a dielectric layer using double patterning and fill techniques, where power-carrying wires are made of low-electromigration materials and signal-carrying wires are made of low-resistivity materials, with specific wire geometries and via structures to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refractory metals are used to reduce electromigration, then reliability is improved, but bulk resistivity increases leading to higher interconnect delay
Solution Approach 1:
The patent applies different metal materials to different wire locations based on their function: copper is used in signal-carrying wires where low resistivity is critical, while refractory metals (tungsten, cobalt, molybdenum) are used in power-carrying wires where electromigration resistance is critical. This local differentiation resolves the contradiction by optimizing each wire type for its primary requirement rather than using a single material for all wires.
2Productivity
If feature size is scaled down to increase integration density, then productivity is improved, but electromigration becomes more prominent due to increased power density
Solution Approach 1:
As devices are scaled to 50nm and below, power density increases making electromigration more severe. The patent addresses this by selectively applying refractory metals in power-carrying interconnects at these scaled dimensions, while maintaining copper in signal wires. This localized material selection allows continued scaling for productivity while maintaining reliability in power-critical paths.
3Manufacturing precision
If double patterning and fill techniques are used to form parallel wires of different materials, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: first forming signal wires with copper using initial patterning, then using spacer-based pitch division to define power wire locations, and finally filling power wires with refractory metals. This segmentation of the manufacturing process enables precise formation of different material wires while managing process complexity through systematic, multi-step fabrication.
Solution Approach 2:
The patent uses spacer-based pitch division which adds a dimensional aspect to pattern formation. Spacers are deposited conformally on patterned features and then anisotropically etched to create additional patterns in a perpendicular dimension, enabling precise placement of power and signal wires without requiring direct lithographic patterning of all features.
Data Source
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AI summary
An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.