Parallel Semiconductor Wiring Board Layout for Gate Stability
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Solution Overview
Problem
Existing wiring boards for driving multiple semiconductor elements connected in parallel face challenges in maintaining consistent wiring length, leading to increased parasitic inductance and potential gate oscillation phenomena, which affect the reliability and performance of the semiconductor elements.
Innovation Solution
The proposed wiring board configuration includes a pair of hard substrates and a soft substrate sandwiched between them, with specific electrode and wiring arrangements that allow for adjustable wiring lengths and reduced parasitic inductance, eliminating the need for connectors and thereby enhancing reliability and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wiring boards for driving multiple semiconductor elements connected in parallel are used, then the semiconductor elements can be driven by a single driving circuit, but the wiring length becomes inconsistent leading to increased parasitic inductance and gate oscillation
Solution Approach 1:
The wiring board is divided into multiple independent wiring regions, each dedicated to a specific semiconductor element. Each wiring region includes separate first and second wirings that connect the control terminal and reference potential terminal respectively, ensuring consistent wiring length within each segment while allowing the overall board to drive multiple elements in parallel
Solution Approach 2:
Each wiring region is designed with localized wiring patterns that ensure consistent wiring length specifically for that region's semiconductor element. The first wiring connects the control terminal and the second wiring connects the reference potential terminal with controlled local path lengths, reducing parasitic inductance at each local connection point
2Reliability
If wiring length is not consistent, then parasitic inductance increases and gate oscillation occurs, but adjusting wiring length requires complex routing through different boards
Solution Approach 1:
Multiple wiring regions are merged into a single integrated wiring board structure. The first wirings and second wirings for multiple semiconductor elements are combined on the same board with coordinated routing patterns, allowing consistent wiring length to be achieved across all elements without requiring complex inter-board routing
Solution Approach 2:
The wiring board utilizes a multi-dimensional layout approach where first wirings and second wirings are arranged in different spatial dimensions and layers. This allows wiring length adjustment and optimization without requiring complex routing through different boards, as the additional dimensional space enables straightforward path planning
3Ease of manufacture
If connectors are used to connect substrates, then assembly is simplified, but connection reliability decreases due to poor contact and mechanical vibration
Solution Approach 1:
The wiring board integrates multiple wiring regions and connection points into a single unified substrate structure. This eliminates the need for separate connectors to join multiple substrates, as all wiring connections are established directly on the integrated board, maintaining both assembly simplicity and connection reliability
Solution Approach 2:
The connector components are extracted and removed from the system. The wiring board design directly provides connection capabilities through its integrated structure, eliminating the intermediate connector elements that would otherwise be needed to join substrates, thereby removing the source of connection reliability issues
Data Source
AI summary
A wiring board includes a pair of hard substrates provided for each of a plurality of semiconductor elements connected in parallel; a soft substrate provided so as to be at least partially sandwiched between all of the pairs of hard substrates; a first electrode configured to connect a control terminal of the semiconductor element and the hard substrate or the soft substrate; a second electrode configured to connect a reference potential terminal of the semiconductor element and the hard substrate or the soft substrate; a first wiring configured to connect in parallel the first electrodes of each of the plurality of semiconductor elements, at least part of the first wiring being provided on the soft substrate; and a second wiring configured to connect in parallel the second electrodes of each of the plurality of semiconductor elements, at least part of the second wiring being provided on the soft substrate.