Parallel Write Data Distribution in NAND Flash Memory
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Solution Overview
Problem
The increasing demand for higher storage capacity in NAND flash memory systems, particularly with quadruple level cell (QLC) technology, leads to a significant increase in the required capacity of volatile memory in controllers, hindering the integration and efficiency of data writing processes due to the need for two-stage writing and interference reduction between cells.
Innovation Solution
A memory system architecture that includes multiple dies with both nonvolatile and volatile memory components, where the controller writes data in parallel to both a write target die and a non-write target die, allowing for reduced volatile memory capacity by utilizing page buffers across multiple dies to manage data storage and reduce the need for extensive buffer memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written to a large number of memory cells during the period after data has been written to a target memory cell until the data is rewritten to the same memory cell, then the storage capacity of volatile memory in the controller increases, but the degree of integration deteriorates
Solution Approach 1:
The patent divides the volatile memory system into multiple separate page buffers located in different dies. Instead of requiring one large volatile memory in the controller, the data is segmented and stored across multiple smaller page buffers distributed in the memory device itself, reducing the controller's volatile memory capacity while maintaining functionality.
Solution Approach 2:
The patent moves the volatile memory function from a single-dimension controller architecture to a multi-dimension distributed architecture. Page buffers are placed in multiple dies (first die, second die, etc.), creating a spatial distribution across dimensions. This allows the system to achieve the required storage capacity without increasing the controller's volatile memory, thereby improving integration.
2Reliability
If two-stage writing is performed to avoid interference between cells, then data integrity is improved, but the required capacity of volatile memory increases
Solution Approach 1:
The patent implements preliminary action by pre-writing data to a first page buffer in the target die, then using a second page buffer in a non-target die as a temporary storage during the rewriting process. This preliminary setup of distributed buffers eliminates the need for the controller to hold data in volatile memory throughout the entire two-stage writing process, reducing volatile memory capacity requirements while maintaining data integrity.
Solution Approach 2:
The patent introduces an intermediary page buffer in a non-target die that acts as a mediator during the two-stage writing process. Instead of requiring the controller's volatile memory to hold data until rewriting is complete, the intermediary buffer in the memory device itself temporarily stores the data, reducing the controller's volatile memory burden while ensuring data integrity throughout the process.
3Object-affected harmful factors
If data is stored in volatile memory in the controller until the second writing is completed, then interference between cells is avoided, but the efficiency of data writing deteriorates
Solution Approach 1:
The patent enables the memory device to serve itself during the writing process. Instead of requiring the controller to continuously hold data in volatile memory and manage the two-stage writing, the memory device's own page buffers handle the temporary storage and data management. This self-service approach eliminates the controller's volatile memory bottleneck and improves writing efficiency while still preventing cell interference through the distributed buffer architecture.
Solution Approach 2:
The patent achieves continuity of useful action by enabling parallel operations. While data is being written to the first page buffer in the target die, the controller can simultaneously prepare data for the second stage and utilize other page buffers in non-target dies. This continuous utilization of resources eliminates idle time in the writing process, improving overall efficiency while maintaining the two-stage writing protocol to prevent interference.
Data Source
AI summary
A memory system includes a first die, a second die, and a controller that controls writing and reading of data to and from the first die and the second die. The first die includes a first nonvolatile memory and a first volatile memory, and the second die includes a second nonvolatile memory and a second volatile memory. The controller includes a third volatile memory and during writing of data into the first die, the controller writes the data, which is stored in the third volatile memory and is to be stored in the first die, to the first volatile memory of the first die and the second volatile memory of the second die in parallel.