Parallel XOR ECC Encoder for One-Clock-Cycle Memory Encoding

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Solution Overview

Problem

Nonvolatile memory devices, such as NAND-type flash memory, PCRAM, MRAM, NFGM, and RRAM, face data error issues due to cell-to-cell interference and narrow read margins, necessitating effective error correction codes (ECC) to ensure reliability, particularly in high-error-rate scenarios.

Innovation Solution

An ECC encoder utilizing exclusive OR (XOR) gates performs ECC encoding in one clock cycle to generate parity data, forming an n-bit codeword with k-bit original data and (n-k)-bit parity, implemented in a memory controller for both writing and reading data to correct errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ECC encoding methods are used, then error correction capability is provided, but encoding time exceeds one clock cycle reducing productivity

Engineering Contradiction:

Improveerror correction capabilityVSAvoidencoding speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The ECC encoding process is segmented into multiple parallel paths, each handling a portion of the parity bit generation. The encoder divides the k-bit data into segments and processes them simultaneously through separate XOR gate networks, allowing the complete encoding to finish within one clock cycle rather than requiring sequential processing across multiple cycles.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The encoding architecture transitions from sequential time-based processing to parallel spatial processing. By arranging XOR gates in a multi-dimensional parallel structure where multiple encoding operations occur simultaneously across different data bits, the system achieves one-clock-cycle encoding while maintaining comprehensive error correction capability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If parallel XOR operations are implemented for one-clock-cycle encoding, then encoding speed increases, but device complexity increases

Engineering Contradiction:

Improveencoding speedVSAvoidencoder circuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Multiple XOR gate operations that would traditionally be executed sequentially are merged into a single clock cycle through parallel circuit implementation. The encoder combines multiple data bits and parity bit calculations into a unified parallel processing structure, achieving high-speed encoding while managing circuit complexity through systematic integration of the XOR gate network.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The encoder uses replicated XOR gate structures for different data bit positions, creating parallel copies of the encoding logic. Each copy processes a specific segment of the input data simultaneously, enabling one-clock-cycle encoding. This copying approach standardizes the circuit design and makes the complexity manageable through repetition of proven modular units.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS10741212B2Error correction code (ECC) encoders, ECC encoding methods capable of encoding for one clock cycle, and memory controllers including the ECC encoders

Publication Date: 2020.08.11 SK HYNIX INC

AI summary

An error correction code (ECC) encoder includes a plurality of exclusive OR (XOR) gates configured to receive a “k”-bit original data in parallel and configured to perform a plurality of XOR operations to the “k”-bit original data to output a “(n−k)”-bit parity data. The “k”-bit original data and the “(n−k)”-bit parity data form an “n”-bit codeword, “k” denotes a natural number and “n” denotes a natural number which is greater than “k”.