Parallel Processing Error Detection via Zero Core Comparison

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Solution Overview

Problem

Existing parallel processing systems face challenges in detecting and correcting errors, particularly in multiplication calculations involving zero operands, which can lead to inefficiencies and inaccuracies, especially in sparse matrix calculations and GPU processing.

Innovation Solution

The method involves identifying zero cores among multiple cores performing multiplication calculations, comparing results between zero and non-zero cores to detect errors, and re-performing calculations in affected cores to correct faults and isolate faulty cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple cores perform multiplication calculations in parallel, then processing speed is improved, but error detection capability deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoiderror detection capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent creates a copy of the multiplication calculation by having a zero core perform the same calculation as a non-zero core. This copy is then used for error detection through comparison, allowing the system to maintain high processing speed while enabling error detection in parallel operations.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent implements a feedback mechanism where calculation results from zero cores and non-zero cores are compared. When discrepancies are detected, the system triggers error correction procedures, creating a closed-loop feedback system that maintains reliability without sacrificing parallel processing speed.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If zero cores are identified and used for error detection, then calculation accuracy is improved, but computational overhead increases

Engineering Contradiction:
Improvecalculation accuracyVSAvoidcomputational overhead
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent makes zero cores serve dual purposes: their original function of processing zero operands and an additional function of error detection through comparison with non-zero cores. This self-service approach allows error detection without adding dedicated error detection hardware, reducing overall system complexity.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent assigns multiple functions to zero cores - they both perform their original multiplication calculations with zero operands and simultaneously serve as error detection units by comparing results with non-zero cores. This multi-functionality improves calculation accuracy without proportionally increasing computational overhead.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If faulty cores are isolated through re-performing calculations, then system reliability is improved, but processing time increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs error detection during the normal parallel processing operation itself, rather than as a separate post-processing step. By having zero cores and non-zero cores simultaneously perform calculations and compare results in real-time, the system identifies faulty cores during processing, minimizing additional time overhead while maintaining high system reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250156188A1Apparatus and method for parallel processing
Publication Date: 2025.05.15 RES & BUSINESS FOUND SUNGKYUNKWAN UNIV
  • US20250156188A1 patent drawing
  • US20250156188A1 patent drawing
  • US20250156188A1 patent drawing

AI summary

There is provided a method of operating an apparatus for parallel processing including multiple cores, comprising: searching for a zero core among the multiple cores performing multiplication calculations to process a first instruction, wherein the zero core includes at least one operand of the multiplication calculations performed by each of the multiple core that is zero; performing multiplication calculations in each of the multiple cores, wherein at least one zero core performs the multiplication calculations for same operands as operands of a non-zero core, wherein the non-zero core includes operand that is not zero; and comparing a calculation result of the at least one zero core with a calculation result of the non-zero core to determine whether calculation error has occurred.