Parallel Zero-Skipping Compression for Random-Access Bit Streams

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Solution Overview

Problem

Current multichannel data compression and decompression algorithms are serial processes that handle only one data bit stream at a time, inefficiently handling data with many zeros in neural inference accelerator hardware, which leads to high power consumption and storage inefficiencies in DRAM and SRAM.

Innovation Solution

A data compression system utilizing a zero-value remover, zero bit mask generator, multiplexers, and row-pointer generator to process multiple bit streams in parallel, removing zeros, generating masks, and packing data for efficient storage and retrieval, with a butterfly shuffler for permutation and unpacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If serial compression algorithms are used to handle one data bit stream at a time, then the compression process is simple to implement, but the processing speed and productivity are low

Engineering Contradiction:
Improveprocessing speedVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the multichannel data stream into multiple independent channels, with each channel processed by a dedicated compression unit. This segmentation enables parallel processing of multiple channels simultaneously, dramatically improving processing speed while keeping each individual compression unit relatively simple in structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent combines multiple compression units into a single integrated parallel compression system that processes multiple channels concurrently. By merging identical functional units and operating them in parallel, the system achieves high productivity while maintaining manageable complexity through modular design

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If zero values are removed from data streams to reduce storage size, then the storage requirements decrease, but the device complexity increases due to additional components needed for zero removal and mask generation

Engineering Contradiction:
Improvestorage sizeVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent extracts zero values from the data streams and separates them from non-zero values. By removing only the zero elements and storing just the non-zero values along with their position information, the system significantly reduces storage requirements while using dedicated circuitry that efficiently handles the extraction process

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces zero bit masks as intermediary data structures that track the positions of zero values. These masks serve as mediators between the original data and the compressed storage format, enabling efficient reconstruction during decompression while keeping the overall system complexity manageable through structured intermediate representation

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If parallel processing of multiple bit streams is implemented, then the productivity increases, but the device complexity increases due to multiple multiplexers and memory access control

Engineering Contradiction:
Improveparallel processing capabilityVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the parallel processing system into distinct functional units: zero-value removers for each channel, multiplexers for data packing, and memory access controllers. This segmentation allows parallel operation while keeping each unit's logic relatively simple and manageable

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from serial processing to parallel processing by adding the dimension of time concurrency and channel multiplicity. Multiple channels are processed simultaneously across different spatial units (multiplexers and memory interfaces), achieving high productivity through dimensional expansion of the processing architecture

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11152952B2Channel-parallel compression with random memory access
Publication Date: 2021.10.19 SAMSUNG ELECTRONICS CO LTD
  • US11152952B2 patent drawing
  • US11152952B2 patent drawing
  • US11152952B2 patent drawing

AI summary

A data compressor includes a zero-value remover, a zero bit mask generator, a plurality of multiplexers, and a row-pointer generator. The zero-value remover receives 2N bit streams of values and outputs 2N non-zero-value bit streams having zero values removed. The zero bit mask generator generates a zero bit mask for a predetermined number of values of each bit stream that indicates a location of a zero value in the predetermined number of values corresponding to the zero bit mask. Each input of a multiplexer in a first column of the multiplexers receives a respective bit stream of the 2N bit streams of non-zero values. The multiplexers in a last column outputting 2N bit streams of values as packed non-zero values in which each output bit stream has a same bit-stream length. The row-pointer generator generates a row-pointer for each respective non-zero-value bit stream in a group of packed non-zero values.