Parallel ZQ Calibration Circuit for Multi-Chip Memory Timing
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Solution Overview
Problem
In multi-chip memory packages, the time required for ZQ calibration operations is excessively long due to the need to perform sequential calibrations for each memory chip, which increases the overall calibration time.
Innovation Solution
A ZQ calibration circuit and method that utilize a first and second calibration circuit, each operating based on different logic levels of a clock signal, allowing simultaneous calibration of multiple memory chips, thereby reducing the total calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential ZQ calibration operations are performed for each memory chip, then calibration accuracy is ensured, but calibration time becomes excessively long
Solution Approach 1:
The calibration system is segmented into multiple independent calibration circuits (first calibration circuit and second calibration circuit), each capable of performing ZQ calibration operations independently on different memory chips. This segmentation allows parallel execution of calibration operations across multiple chips simultaneously, reducing total calibration time while maintaining individual calibration accuracy through dedicated comparison and control circuits for each channel
Solution Approach 2:
Multiple calibration circuits are merged into a unified calibration system that shares common control logic and timing mechanisms. The first and second calibration circuits operate in parallel under coordinated control, enabling simultaneous calibration of multiple memory chips while maintaining systematic control over the calibration process, thus achieving both time reduction and accuracy preservation
2Loss of time
If multiple memory chips are calibrated simultaneously, then calibration time is reduced, but circuit complexity increases
Solution Approach 1:
The complex task of calibrating multiple chips is segmented into separate, identical calibration circuits, each handling one chip. This modular segmentation distributes the complexity across multiple independent units rather than concentrating it in a single complex circuit, making the overall system more manageable and easier to implement while enabling parallel operation
Solution Approach 2:
The calibration circuit design is copied to create multiple identical calibration channels (first calibration circuit and second calibration circuit). Each copy performs the same calibration function independently, allowing simultaneous calibration of multiple chips without requiring complex inter-chip coordination logic within each individual calibration path, thus controlling complexity through replication of simple, proven designs
Data Source
AI summary
Provided are a ZQ calibration circuit and a ZQ calibration method. The ZQ calibration circuit includes: a first calibration circuit; and a second calibration circuit sharing a first ZQ voltage with the first calibration circuit, wherein the first ZQ voltage is generated from a ZQ pad connected to an external resistor. The first calibration circuit includes: a first comparator; a second comparator; a first pull-up counter; a first pull-up driver; and a first switch electrically interconnecting the first pull-up counter. The second calibration circuit includes: a third comparator; a fourth comparator; a second pull-up counter; a second pull-up driver; and a second switch connected to the second pull-up counter and turned on based on a second logic level of the clock signal to electrically interconnect the second pull-up counter and the second pull-up driver.