Paralleled Phase Leg Switches Gate Drive Control
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Solution Overview
Problem
Inverters for electrified vehicles face significant switching losses due to common source inductance, which are exacerbated when operating at lower load currents, leading to inefficient energy conversion and reduced fuel economy.
Innovation Solution
Implementing separate gate drive signals for paralleled power switching devices, allowing a subset to perform hard-switching and another subset to perform soft-switching, optimizing aggregate switching losses by adjusting the number of transistors involved based on phase current magnitude, thereby enhancing common source inductance effects across a range of load conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If separate gate drive signals are implemented for paralleled power switching devices, then switching losses are reduced especially at low current levels, but device complexity increases
Solution Approach 1:
The gate drive signal is segmented into multiple independent signals (first gate drive signal and second gate drive signal) that can be applied separately to different subsets of paralleled power switching devices. This allows selective control of switching behavior for different device groups, enabling optimization of switching losses at various current levels while maintaining manageable complexity through modular signal generation.
Solution Approach 2:
The gate drive signals are made dynamic by adjusting their timing and characteristics based on operating conditions, particularly phase current magnitude. The system transitions between different switching modes (hard-switching and soft-switching) depending on current levels, allowing optimal switching loss reduction across the full operating range while adapting the control strategy to match actual load conditions.
2Power
If all paralleled transistors are hard-switched simultaneously, then current handling capability is maximized, but switching losses increase significantly
Solution Approach 1:
The paralleled transistor set is segmented into multiple subsets, each controlled by separate gate drive signals. This allows different subsets to operate in different switching modes simultaneously - some performing hard-switching for maximum current handling while others perform soft-switching for reduced losses, achieving both high power capability and efficient energy usage.
Solution Approach 2:
The switching parameters (timing, duration, sequence) of different gate drive signals are dynamically adjusted based on operating conditions. By changing these parameters, the system can optimize the balance between current handling capability and switching loss reduction for each transistor subset, achieving both objectives across various operating points.
3Loss of energy
If enhanced common source inductance is used, then switching time is reduced and switching loss is reduced, but the beneficial effect diminishes at lower load currents
Solution Approach 1:
The gate drive signals are made adaptive and dynamic, changing their characteristics based on detected current levels. At higher currents, the enhanced common source inductance provides natural soft-switching benefits. At lower currents, the control system dynamically adjusts the gate drive signals to maintain optimal switching behavior, ensuring the beneficial effects are preserved across the full current range from high to low load conditions.
Solution Approach 2:
The switching parameters controlled by the gate drive signals are adjusted based on operating conditions. By changing timing, duration, and sequence parameters dynamically, the system compensates for the reduced effectiveness of enhanced common source inductance at low currents, maintaining optimal switching loss reduction across all current levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces switching losses significantly, especially at low current levels, improving energy efficiency and fuel economy by maintaining the beneficial impact of enhanced common source inductance across a broader range of operating conditions.
Implementation Method 1
Common source inductance refers to an inductance shared by the main power loop (i.e., the drain-to-source or collector-to-emitter power output of the transistor) and the gate driver loop (i.e., gate-to-source or gate-to-emitter) in a power switching transistor.
Implementation Method 2
Pulse Width Modulation (PWM) control signals are applied to drive the gates of the IGBTs in order to turn them on and off as necessary.
Data Source
AI summary
An electrified vehicle propulsion system uses current feedback to modify gate drive signals to suppress voltage spikes and increase switching efficiency. A DC link having a link capacitor and a link inductance is connected to first and second converters. A first converter bridge has a first phase leg with first upper and lower switching devices, each switching device having a respective gate loop. A second converter bridge has a second phase leg with second upper and lower switching devices, each switching device having a respective gate loop. A plurality of gate drivers provide gate drive signals to respective gate loops for turning the respective switching devices on and off. A plurality of gate coils are provided, wherein each gate coil is connected in series between a respective gate driver and a respective gate loop. Each gate coil is respectively inductively coupled to the link inductance.