Paralleled Transistor Cells With Resistive Gate Decoupling
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Solution Overview
Problem
Silicon Carbide (SiC) transistors switch faster than Silicon transistors but experience secondary effects like noise, electromagnetic interference, overvoltage, overheating, and short circuits, which conventional methods attempt to manage by slowing switching speed, increasing cost and reducing efficiency.
Innovation Solution
Resistively decoupling the gate of paralleled transistor cells in power semiconductor devices to delay turn-OFF, thereby increasing turn-OFF time and reducing susceptibility to short circuits, while maintaining switching performance and reducing cost by eliminating or reducing filter components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional methods are used to slow switching speed to reduce secondary effects, then noise and electromagnetic interference are reduced, but device complexity and cost increase due to additional components
Solution Approach 1:
The transistor is divided into multiple paralleled cells with different gate structures. Each cell can be independently controlled through its gate structure, allowing selective turning off of cells to manage secondary effects without requiring external components. The segmentation enables gradual reduction of harmful effects while maintaining device simplicity.
Solution Approach 2:
Different gate structures are applied to different cells within the transistor array. Some cells have gate structures with higher resistance or capacitance values, creating local variations in switching characteristics. This local quality differentiation allows certain cells to switch slower and reduce electromagnetic interference while others maintain fast switching, achieving noise reduction without adding external components.
2Reliability
If turn-OFF time is increased to reduce secondary effects, then overvoltage and short circuit susceptibility are reduced, but switching speed and efficiency deteriorate
Solution Approach 1:
The transistor is segmented into multiple cells that can be turned off at different rates. By controlling the gate structures of individual cells, the overall turn-OFF process is extended in time, reducing voltage spikes and short circuit risk. Meanwhile, other cells maintain fast switching, preserving overall productivity and efficiency.
Solution Approach 2:
The switching characteristics of different cells are made dynamic through varied gate structures. During turn-OFF, cells with higher resistance/capacitance gates switch slower, dynamically extending the turn-OFF time to reduce stress. During turn-ON, all cells can switch quickly, maintaining high switching speed and efficiency. This dynamic behavior resolves the contradiction between reliability and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies gate drive operations, increases performance, reduces cost, and enhances reliability by providing a softer turn-OFF, reducing high-speed switching effects and susceptibility to short circuit damage, while maintaining efficiency and protecting the device from secondary effects.
Implementation Method 1
Resistively decoupling the gate of paralleled transistor cells in power semiconductor devices to delay turn-OFF
Data Source
AI summary
An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.