Application Parallelism Assessment via Execution Path Simulation
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Solution Overview
Problem
Current technologies lack a method to assess application design at a high level using data flow and data abstraction diagrams, such as UML diagrams, to effectively exploit parallelism in electronic systems, which is crucial for optimizing compute and memory bandwidth in complex software applications.
Innovation Solution
A computerized system and method for application modeling that includes a user interface, memory, and processors to receive an application specification, extract nodes, analyze execution dependencies, determine application execution paths, and simulate these paths on a computational platform to generate a report on parallelism, allowing for optimized resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If application-level parallelism is exploited to improve performance, then compute and memory bandwidth utilization is improved, but the complexity of assessing and optimizing parallelism at high-level design increases
Solution Approach 1:
The patent segments the application design assessment into distinct analysis dimensions (temporal parallelism and spatial parallelism) that can be independently evaluated. This allows complex parallelism optimization to be broken down into manageable components that can be assessed separately and combined, reducing the overall complexity of the assessment process.
Solution Approach 2:
The patent introduces an intermediary assessment framework that acts as a mediator between high-level application design and parallel execution optimization. This framework provides structured methodologies and tools that translate design specifications into parallelism assessments without requiring direct complex analysis of the entire application, thereby reducing assessment complexity.
2Ease of operation
If high-level application design assessment methods are developed, then the ease of assessing parallelism is improved, but the device complexity increases due to additional analysis capabilities
Solution Approach 1:
The patent creates a universal assessment framework that can evaluate multiple types of parallelism (temporal and spatial) using a unified methodology. This multi-functional approach allows the same assessment tools and processes to be applied across different application domains and design levels, improving ease of use while avoiding the need for separate complex analysis systems for each parallelism type.
Solution Approach 2:
The assessment framework is designed to automatically extract and analyze parallelism characteristics from high-level design specifications without requiring extensive manual intervention or complex external analysis tools. The system serves itself by using the design documentation as input and generating parallelism assessments automatically, thereby improving ease of operation without proportionally increasing device complexity.
Data Source
AI summary
A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources. The operations may include determining and simulating a plurality of application execution paths on a computational platform for generating a report including an analysis of the application algorithm.