Software Parallelization Scoring for Hardware Architecture Selection
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Solution Overview
Problem
Existing methods for determining the most suitable hardware architecture for software applications are tedious, expensive, and require detailed knowledge of the target architecture and programming language, necessitating multiple trials and code adaptation.
Innovation Solution
A method that determines a hardware architecture by executing a software application with varying input data sets, calculating a parallelization score based on output changes, and selecting the architecture using a table associating score ranges with hardware types, without needing to know the hardware or programming language specifics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic program analysis is used to determine suitable hardware architecture, then accurate evaluation of application performance is achieved, but the process becomes tedious and expensive requiring detailed knowledge of target architecture and programming languages
Solution Approach 1:
The patent introduces an intermediary metric calculation system that automatically evaluates application characteristics without requiring expert knowledge. The system uses intermediate metrics (execution time, resource consumption, parallelization potential) as mediators between the application code and hardware architecture selection, replacing the need for dynamic program analysis by human experts.
Solution Approach 2:
The method enables self-service by allowing the system to automatically determine suitable hardware architecture through automated metric calculation and evaluation. The application itself provides the necessary information through its execution characteristics, eliminating the need for external expert analysis and making the process self-sufficient.
2Reliability
If multiple execution tests are performed on different target hardware architectures, then the most suitable architecture is identified, but the process becomes expensive and time-consuming
Solution Approach 1:
The patent applies preliminary action by calculating key metrics (execution time, resource consumption, parallelization potential) in advance during a single test execution. These pre-calculated metrics are then used to evaluate multiple hardware architectures without requiring actual execution tests on each target platform, significantly reducing time and cost while maintaining selection accuracy.
Solution Approach 2:
The method creates a virtual model or copy of the evaluation process by using metric-based simulation instead of physical execution tests. The system copies the essential characteristics of multiple hardware architectures and evaluates the application against these models through calculated metrics, avoiding the need for actual multiple execution tests.
3Productivity
If application code is analyzed in detail to evaluate parallel operation possibilities, then optimal parallelization is achieved, but the process requires detailed knowledge of the application structure and becomes complex
Solution Approach 1:
The patent replaces manual code analysis (mechanical process requiring human expertise) with an automated metric calculation system. The system substitutes the mechanical process of detailed code inspection with automated calculation of parallelization potential metrics, maintaining the ability to evaluate parallel operation possibilities while eliminating the need for detailed code analysis by humans.
Data Source
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AI summary
The invention relates to a method for determining a target hardware architecture suitable for a software application, the method comprising steps consisting in: defining a first input data set (ID0) of the application (AL2); executing the application by a processor (PRC) from the first input set to obtain a first output data set (OD0); executing several iterations each comprising: selecting an input data item; generating a second input set (ID1, ID2) from the first input set, by modifying the selected input data item; executing the application from the second input set to obtain a second output set (OD1, OD2); and calculating a metric relating to the first and second input and output sets of the iteration; calculating a parallelization score (PS) from the metrics calculated at each iteration; and determining the target architecture according to the parallelization score.