Parallelizing Cryptographic Algorithms for CPU Offloading
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Solution Overview
Problem
Cryptographic algorithms are computationally intensive, impacting system performance and battery life on modern platforms, necessitating a method to accelerate cryptographic processing while maintaining information security.
Innovation Solution
A cryptographic algorithm is parallelized by breaking it into components, distributing processing to one or more parallelized devices such as a graphics processing unit or cryptographic co-processor, depending on parallelizability, to offload processing from the central processing unit and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic algorithms are implemented in software on a CPU core, then information security is maintained, but system performance is impacted and battery life is reduced
Solution Approach 1:
The cryptographic algorithm is divided into multiple components or blocks that can be processed independently and in parallel. This segmentation allows the computationally intensive cryptographic operations to be distributed across multiple processing units, thereby improving system performance while maintaining security through complete execution of all algorithmic steps.
Solution Approach 2:
A parallelized processing device is introduced as an intermediary between the CPU and the cryptographic algorithm execution. This intermediary handles the computationally intensive parallelizable portions of the algorithm, offloading work from the CPU and improving overall system performance while the CPU maintains control over the cryptographic process to ensure security.
2Reliability
If cryptographic algorithms are implemented in software on a CPU core, then information security is maintained, but battery life is reduced
Solution Approach 1:
By segmenting the cryptographic algorithm into parallelizable and non-parallelizable components, the system can distribute work efficiently across processing units. The parallelizable portions are executed on dedicated hardware that can perform operations more energy-efficiently, reducing overall power consumption while maintaining complete algorithm execution for security.
Solution Approach 2:
The patent replaces the general-purpose CPU software implementation with a specialized parallelized processing device for executing cryptographic algorithms. This substitution uses hardware-based parallel processing that is more energy-efficient for cryptographic operations, reducing battery consumption while maintaining security through deterministic execution of all algorithmic steps.
3Productivity
If cryptographic algorithms are parallelized and distributed to parallelized devices, then processing performance is improved, but device complexity increases
Solution Approach 1:
The cryptographic algorithm is segmented into distinct components with clear boundaries between parallelizable and non-parallelizable portions. This segmentation provides a structured approach to parallelization that manages complexity by organizing the algorithm into manageable units that can be independently processed while maintaining overall system coherence.
Solution Approach 2:
The system applies partial parallelization by identifying and parallelizing only the portions of the cryptographic algorithm that can be safely executed in parallel, while keeping non-parallelizable components sequential. This selective approach achieves performance improvement without requiring complete restructuring of the entire algorithm, thus managing device complexity more effectively.
Data Source
AI summary
A method, an apparatus, and a non-transitory computer readable medium for accelerating cryptographic processing are presented. A cryptographic algorithm is parallelized, which includes breaking the cryptographic algorithm into components, parallelizing an entire component if the component is fully parallelizable, parallelizing part of a component if the component is partially parallelizable, and sequentially executing a component if the component is not parallelizable. Processing of the parallelizable component or the partially parallelizable component is distributed to one or more parallelized devices. The parallelized devices include at least one of: a graphics processing unit or a cryptographic processing device, which may include an integrated cryptographic processor or a cryptographic co-processor.


