Parallelized Multiple Dispatch System for Microprocessor Queue Arbitration
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Solution Overview
Problem
Superscalar microprocessors face challenges in dispatching multiple instructions in parallel while maintaining arbitration priority and meeting timing requirements, as the serialized determination of ready instructions fails to meet the necessary speed for concurrent dispatch.
Innovation Solution
A parallelized multiple dispatch system that divides an ordered queue into N groups, where qualify logic determines readiness, ordered select logic identifies the oldest candidate in each group, and dispatch logic sends candidates from each group in parallel, with shift logic maintaining order by filling vacant entries without altering the remaining candidates' order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the oldest candidate instruction is determined first in a serialized manner, then the arbitration priority order is maintained, but the timing requirements cannot be met when dispatching multiple instructions
Solution Approach 1:
The ordered queue is divided into N groups, where each group contains every Nth entry (e.g., group 0 contains entries 0, N, 2N, ..., group 1 contains entries 1, N+1, 2N+1, ...). This segmentation allows parallel determination of oldest candidates within each group while maintaining the overall order across all groups, resolving the contradiction between maintaining arbitration priority and meeting timing requirements for multiple instruction dispatch.
2Productivity
If multiple instructions are dispatched from a single reservation station queue, then instruction parallelism is increased, but the hardware complexity for determining next oldest candidates increases
Solution Approach 1:
By segmenting the ordered queue into N groups, the hardware complexity is distributed across parallel pathways rather than requiring a single complex serialized comparison unit. Each group can be processed independently with simpler logic, and the overall system achieves multiple instruction dispatch capability through this modular segmentation approach.
Solution Approach 2:
The problem of finding the oldest candidate among many instructions is transformed from a single-dimensional serialized search into a multi-dimensional parallel structure. By organizing candidates into N groups and processing them in parallel dimensions, the system achieves O(N) parallel operations instead of O(N^2) serialized comparisons, reducing hardware complexity while maintaining productivity.
Data Source
AI summary
A parallelized multiple dispatch ordered queue including an ordered queue, qualify logic, ordered select logic, and dispatch logic. The ordered queue stores candidates in order from oldest to youngest into multiple entries. The ordered queue is divided into N groups in which an i'th group includes every i'th entry of every N entries of the ordered queue, wherein i is an integer less than or equal to N. The qualify logic determines whether any candidate is ready to be dispatched. The ordered select logic respectively determines the oldest candidate in each group that is ready to be dispatched. The dispatch logic dispatches the oldest ready candidates in parallel. The shift logic shifts the stored candidates in the ordered queue to fill any vacant entries between remaining ones of the stored candidates without changing an order of the remaining ones of the stored candidates in the ordered queue. The ordered queue may have any size or depth and N is any suitable integer determining the number of candidates (e.g., instructions) that may be dispatched in parallel.