Parallelized Ingress Compute Architecture for Network Switches

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Solution Overview

Problem

Distributed deep learning systems face significant bottlenecks due to network latency and limited bandwidth, particularly in centralized parameter server architectures and All Reduce methods, which hinder the performance of distributed computing systems.

Innovation Solution

Embedding compute logic within network switches to perform collective actions such as reduction operations on gradients, reducing the need for data to be transmitted to a centralized server by processing compute data within the switch, thereby minimizing communication overhead and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If compute logic is centralized in parameter servers, then system coordination is simplified, but network latency and communication overhead increase

Engineering Contradiction:
Improvesystem coordination complexityVSAvoidnetwork latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments the centralized compute function into distributed compute nodes embedded within network switches. Each switch performs local gradient reduction operations independently, dividing the monolithic parameter server role into multiple distributed units that operate autonomously, thereby reducing network communication latency while maintaining coordination capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimensional approach by embedding compute logic directly within the network switch fabric rather than separating it as a distinct centralized or distributed component. This spatial reorganization allows compute operations to occur at the network edge, reducing the communication dimensions and latency associated with traditional parameter server architectures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If data is transmitted to centralized servers for processing, then processing tasks are simplified, but network bandwidth consumption increases

Engineering Contradiction:
Improveprocessing task complexityVSAvoidnetwork bandwidth consumption
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent extracts the compute function from centralized parameter servers and relocates it to distributed network switches. This extraction eliminates the need to transmit large volumes of gradient data across the network for processing, as the computation occurs locally at the switch level, thereby significantly reducing network bandwidth consumption while maintaining processing capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent enables network switches to perform gradient reduction operations autonomously without requiring external centralized processing. Each switch independently executes compute tasks on locally received gradient data, serving its own processing needs and eliminating the bandwidth overhead of transmitting data to centralized servers for computation.

Inventive Principle:
Principle #25Self-service

3Loss of time

If compute operations are performed at network edges, then communication overhead is reduced, but device complexity increases

Engineering Contradiction:
Improvecommunication overheadVSAvoidswitch architecture complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges the compute logic with the existing network switch architecture, integrating gradient reduction capabilities directly into the switch fabric. This consolidation allows the switch to perform both networking and computation functions using a unified architecture, reducing communication overhead while managing device complexity through functional integration rather than separation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transforms the network switch into a multi-functional device that simultaneously performs packet forwarding and gradient reduction operations. By making the switch universal in its capabilities, the system reduces communication overhead without proportionally increasing complexity, as the same hardware infrastructure supports multiple functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11099902B1Parallelized ingress compute architecture for network switches in distributed artificial intelligence and other applications
Publication Date: 2021.08.24 INNOVIUM INC
  • US11099902B1 patent drawing
  • US11099902B1 patent drawing
  • US11099902B1 patent drawing

AI summary

Distributed machine learning systems and other distributed computing systems are improved by embedding compute logic at the network switch level to perform collective actions, such as reduction operations, on gradients or other data processed by the nodes of the system. The switch is configured to recognize data units that carry data associated with a collective action that needs to be performed by the distributed system, referred to herein as “compute data,” and process that data using a compute subsystem within the switch. The compute subsystem includes a compute engine that is configured to perform various operations on the compute data, such as “reduction” operations, and forward the results back to the compute nodes. The reduction operations may include, for instance, summation, averaging, bitwise operations, and so forth. In this manner, the network switch may take over some or all of the processing of the distributed system during the collective phase.