Parallelized IC Layout Extraction Using Tile Image Pipelines
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Solution Overview
Problem
Current IC layout extraction methods are inefficient due to idle computing resources and late detection of problematic images, leading to re-acquisition of entire batches and tedious repositioning of the microscope field-of-view, especially when dealing with issues like image drift and artifacts during delayering.
Innovation Solution
A parallelized real-time image acquisition and polygon extraction process using multiple concurrent pipelines (image acquisition, layout portion extraction, and comparison) allows for immediate identification and remediation of problematic images, enabling concurrent processing and reducing the need for re-acquiring entire batches by focusing on individual tile images.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional batch processing methods are used for IC layout extraction, then computing resources are fully utilized, but processing time increases and productivity decreases
Solution Approach 1:
The patent divides the IC layout extraction process into multiple independent parallel pipelines: image acquisition pipeline, layout portion extraction pipeline, and comparison pipeline. Each pipeline processes different aspects of the extraction simultaneously, enabling concurrent execution and reducing overall processing time while maintaining full utilization of computing resources.
Solution Approach 2:
The patent transitions from sequential single-threaded processing to multi-threaded parallel processing across multiple dimensions of computation. By implementing concurrent pipelines that operate simultaneously on different data streams (image acquisition, extraction, comparison), the system achieves exponential speedup in layout extraction while effectively utilizing multi-core processing capabilities.
2Reliability
If batch processing is used, then resource utilization is maximized, but problematic images are detected late causing re-acquisition of entire batches
Solution Approach 1:
The patent implements preliminary validation of image quality within the parallel comparison pipeline, checking for drift and artifacts immediately after image acquisition and during the extraction process. This early detection mechanism identifies problematic images before complete batch processing, allowing selective re-acquisition of only affected tiles rather than entire batches.
Solution Approach 2:
The comparison pipeline provides real-time feedback on image quality metrics and extraction accuracy. When drift or artifacts are detected in specific tile images, the system generates feedback signals to trigger selective re-acquisition of only those problematic regions, continuously improving overall process reliability while minimizing time loss.
3Reliability
If entire batches are re-acquired due to problematic images, then comprehensive validation is ensured, but time loss and operational complexity increase
Solution Approach 1:
The patent extracts and isolates only the problematic tile images that require re-acquisition, rather than re-processing entire batches. The system identifies specific tiles with drift or artifact issues and triggers targeted re-imaging of those individual regions, significantly reducing microscope repositioning operations and simplifying the operational workflow while maintaining comprehensive validation.
4Productivity
If sequential processing is used, then system complexity is reduced, but computing resource utilization decreases and productivity drops
Solution Approach 1:
The patent segments the layout extraction system into distinct modular pipelines (image acquisition, layout extraction, comparison) that can execute concurrently. This segmentation enables effective utilization of multi-core processors and accelerators, dramatically increasing processing throughput while the modular architecture keeps system complexity manageable through clear separation of concerns.
Solution Approach 2:
The parallel pipeline architecture implements universal processing capabilities that can handle multiple types of operations simultaneously - image acquisition, various extraction algorithms, and different comparison methods - all within a unified framework. This multi-functionality maximizes computing resource utilization across diverse hardware platforms without proportionally increasing system complexity.
Data Source
AI summary
An integrated circuit (IC) layout extraction method includes executing: an image receiving pipeline that, for each tile n of N tiles of an IC, receives a tile image n of the tile n of the IC acquired using a microscope; a layout portion extraction pipeline that extracts a layout portion n from each received tile image n; and a layout portion comparison pipeline that compares each layout portion n with a corresponding portion of the reference IC layout. The image receiving pipeline, the layout portion extraction pipeline, and the layout portion comparison pipeline are parallel pipelines that are executed by the electronic processor concurrently in time. The extracted layout portions for the N tiles of the IC are combined to form the extracted layout for the IC.