Parallelized Macro-Pipeline for Low-Latency Graphics Rendering

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Solution Overview

Problem

Current graphics processing systems face challenges in reducing motion-to-photon latency, which is critical for low-latency applications like VR, AR, and MR, as existing technologies do not effectively parallelize the graphics pipeline to handle the end-to-end processing efficiently, leading to potential user discomfort and immersion issues.

Innovation Solution

A parallelized macro-pipeline is introduced, which divides the frame into sub-frames and processes them in parallel across the render and post-render stages, including parallelization of encoding, packetization, and transmission, allowing for earlier initiation of post-render stages before the entire frame is rendered, and offloads tasks to the display device for reduced latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the graphics pipeline processes the entire frame sequentially before post-render operations, then processing completeness is ensured, but motion-to-photon latency increases

Engineering Contradiction:
Improvemotion-to-photon latencyVSAvoidprocessing completeness
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The frame is divided into multiple sub-frames, allowing post-render operations to be applied to each sub-frame independently and in parallel with the rendering of remaining sub-frames. This segmentation enables the pipeline to process and output portions of the frame before the entire frame is fully rendered, reducing motion-to-photon latency while maintaining processing completeness through systematic handling of all frame portions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Post-render operations are initiated on early-sub-frames before the entire frame rendering is complete. By performing these operations preliminarily on available sub-frame data, the system reduces the overall processing time from frame start to final output, achieving lower latency without sacrificing the completeness of the full frame processing cycle.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the graphics pipeline is parallelized to reduce latency, then motion-to-photon latency decreases, but device complexity increases

Engineering Contradiction:
Improvemotion-to-photon latencyVSAvoidpipeline structure
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The graphics pipeline is segmented into independent rendering and post-render operation stages that can operate in parallel on different sub-frames. This segmentation creates a structured parallel architecture where each stage handles specific portions of the frame independently, reducing latency through concurrent processing while managing complexity through clear stage separation and defined data flow between stages.

Inventive Principle:
Principle #1Segmentation

3Productivity

If post-render operations wait for complete frame rendering, then processing accuracy is maintained, but productivity decreases

Engineering Contradiction:
Improveframe processing throughputVSAvoidprocessing accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The frame is segmented into sub-frames that can be processed independently through the rendering and post-render stages. This segmentation allows post-render operations to begin on completed sub-frames immediately, improving throughput by eliminating idle wait time, while maintaining processing accuracy through consistent application of operations to each sub-frame portion with proper synchronization to ensure complete frame assembly.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10115223B2Graphics apparatus including a parallelized macro-pipeline
Publication Date: 2018.10.30 INTEL CORP
  • US10115223B2 patent drawing
  • US10115223B2 patent drawing
  • US10115223B2 patent drawing

AI summary

An embodiment of a graphics apparatus may include a frame divider to divide a frame into two or more sub-frames, and a parallelized post-render stage communicatively coupled to the frame divider to process a sub-frame of the two or more sub-frames in parallel with a render operation. The parallelized post-render stage may include a post-processor communicatively coupled to the frame divider to post-process a rendered sub-frame in parallel with the render operation. Other embodiments are disclosed and claimed.