Parallelized SIC Receiver Architecture for Wireless Signal Decoding
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Solution Overview
Problem
Wireless communication receiver systems face challenges in decoding high code rate signals due to increased hardware and software processing demands, which can lead to error vector magnitude (EVM) performance issues, especially with advancements in wireless communication systems and high sampling rate ADC deployments.
Innovation Solution
A wireless receiver architecture employing a parallelized successive interference cancellation (PSiC) technique that encodes multiple analog signals with an orthogonal code set, combines them into a single composite signal, and uses multiple SiC modules to sequentially remove interfering signals, ultimately decoding the signal of interest with reduced EVM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high code rate signals are used to spread data signals across wide bandwidth, then receiver hardware resources can be shared and multiple input signals can be combined into a single signal, but decoding operations require hardware and software elements capable of operating at higher speeds which strains receiver processing resources
Solution Approach 1:
The patent segments the decoding process into multiple parallel Successive Interference Cancellation (SIC) modules, each handling a specific user signal. This segmentation allows the high code rate signal to be processed by dividing it into manageable parallel streams, reducing the processing burden on individual hardware components while maintaining the ability to handle multiple combined signals
2Measurement precision
If high sampling rate ADC is deployed to sample high code rate wideband signals, then signal processing capability is improved, but receiver hardware and software processing resources are strained
Solution Approach 1:
The patent segments the high sampling rate signal processing into parallel SIC modules that operate independently on different user signals. This segmentation allows the system to maintain high sampling accuracy while distributing the processing load across multiple specialized modules, reducing the strain on overall receiver resources
Solution Approach 2:
The patent implements partial processing by having each SIC module focus on canceling interference for a specific user rather than processing the entire wideband signal. This partial action approach maintains measurement precision for each user signal while avoiding the excessive processing resource consumption that would result from processing all signals simultaneously at full resolution
3Productivity
If conventional CDM decoding is used for high code rate signals, then signal decoding can be performed, but Error Vector Magnitude (EVM) performance deteriorates
Solution Approach 1:
The patent applies preliminary action by having SIC modules perform interference cancellation before the final decoding stage. Each SIC module preemptively removes interference from other users' signals, which improves the quality of the signal entering the decoder and thereby improves EVM performance while maintaining decoding throughput
Solution Approach 2:
The patent converts the harmful interference from other users into a beneficial process by using SIC modules to systematically identify and cancel these interfering signals. The interference that would normally degrade EVM performance is instead used as the target for cancellation, transforming a harmful effect into a mechanism for improving signal quality and decoding accuracy
Data Source
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AI summary
The disclosed systems, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a signal encoding module to encode a plurality of received analog signals with an orthogonal code set and combine the encoded analog signals into a single encoded analog composite signal, an analog-to-digital conversion unit to convert the single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals. The presented configurations also include a bank of multiple successive interference cancellation (SiC) modules to sequentially remove the constituent digital signals from the single encoded digital composite signal until a single constituent digital signal remains and a decoding module configured to decode the remaining constituent digital signal from the single encoded digital composite signal.