Parallelizing Compiler for Embedded Systems
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Solution Overview
Problem
The development of next-generation vehicles requires advanced real-time control systems and information systems, which often lead to increased processor calculation loads, making it challenging to improve processing speed without increasing power consumption, and existing methods for parallelizing sequential programs for multicore processors are time-consuming and costly, failing to fully utilize processor capabilities.
Innovation Solution
A parallelizing compile method that divides sequential programs into macro tasks, identifies control and data dependencies, fuses tasks, and performs static scheduling to generate a parallelizing program executable by a multiprocessor system, reducing development time and cost while ensuring high-speed processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of a processor is increased to improve processing speed, then the processing speed is improved, but the power consumption increases in proportion to the cube of the frequency
Solution Approach 1:
The patent divides a sequential program into multiple parallel tasks that can be executed simultaneously on multiple processor cores. This segmentation of computational work allows the system to achieve higher processing speeds by utilizing multiple lower-frequency cores instead of a single high-frequency core, thereby reducing power consumption while maintaining or improving overall processing capability.
2Productivity
If manual parallelization of sequential programs is performed to utilize multicore processors, then processing capability is improved, but the development time and cost increase significantly
Solution Approach 1:
The patent employs an automatic parallelization compiler that performs task division, dependency analysis, and parallel program generation without requiring manual intervention. This self-service approach to parallelization eliminates the time-consuming manual process while still achieving effective utilization of multicore processors, thus improving processing capability without increasing development time.
Solution Approach 2:
The patent replaces the mechanical process of manual program analysis and parallelization with an automated compiler system. This substitution uses computational algorithms to automatically analyze program dependencies, divide tasks, and generate parallel code, thereby eliminating the labor-intensive manual process and significantly reducing development time.
3Productivity
If functions are simply distributed to each processor core to improve throughput, then throughput is improved, but latency is not reduced and processing speed is not significantly improved
Solution Approach 1:
The patent implements dynamic task scheduling and allocation strategies that adapt to the specific dependency structures of the program. By dynamically analyzing control and data dependencies, the system optimally assigns tasks to processor cores, ensuring that both throughput and latency are minimized. This dynamic approach allows for better utilization of parallel processing capabilities compared to simple static distribution.
Data Source
AI summary
A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.