Parallelogram Cell Design for 3D NAND Memory
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Solution Overview
Problem
Three-dimensional memory structures face challenges in increasing bit density while minimizing the negative impacts on power consumption and operational speed due to the need for deep etches and increased number of word line planes and string select lines.
Innovation Solution
The arrangement of pillars on a regular grid with a non-rectangular parallelogram unit cell, where alternating rows of pillars intersect alternating bit lines and a single string select line intersects all pillars in a unit cell, allowing for a higher density of bit lines and reduced number of string select lines, thereby enhancing data rate and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word line planes and string select lines is increased to achieve higher bit density, then storage capacity is improved, but power consumption increases and operational speed decreases
Solution Approach 1:
Multiple string select lines are merged into a single shared string select line that intersects all pillars in a unit cell. This consolidation reduces the total number of string select lines required, thereby reducing power consumption while maintaining the ability to select and access multiple memory strings simultaneously through the shared control mechanism.
Solution Approach 2:
The shared string select line serves multiple functions by simultaneously controlling access to all pillars within a unit cell. This multi-functional approach allows a single control line to manage multiple memory strings, reducing the overall number of control lines needed and improving power efficiency without sacrificing storage capacity.
2Quantity of substance
If the number of word line planes and string select lines is increased to achieve higher bit density, then storage capacity is improved, but operational speed decreases
Solution Approach 1:
Multiple string select lines are merged into a single shared string select line that intersects all pillars in a unit cell. This consolidation reduces the total number of string select lines required, thereby reducing power consumption while maintaining the ability to select and access multiple memory strings simultaneously through the shared control mechanism.
Solution Approach 2:
The shared string select line serves multiple functions by simultaneously controlling access to all pillars within a unit cell. This multi-functional approach allows a single control line to manage multiple memory strings, reducing the overall number of control lines needed and improving power efficiency without sacrificing storage capacity.
3Volume of moving object
If deep etches are used to create vertical channels, then three-dimensional memory structure is achieved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The unit cell employs a non-rectangular parallelogram configuration with alternating rows of pillars shifted relative to each other. This asymmetric arrangement allows bit lines to intersect pillars at optimized positions, reducing the depth and complexity of required etches while maintaining the three-dimensional vertical channel structure and memory functionality.
Solution Approach 2:
The pillar arrangement utilizes lateral shifting between alternating rows to create an optimized geometric configuration. This dimensional adjustment in the lateral plane enables reduced etch depths by positioning pillars where bit lines can access them more efficiently, thereby simplifying the vertical etching process while preserving the 3D memory architecture.
4Ease of manufacture
If traditional rectangular grid arrangement is used, then manufacturing is simplified, but bit line density and data rate are limited
Solution Approach 1:
The unit cell employs a non-rectangular parallelogram configuration with alternating rows of pillars shifted relative to each other. This asymmetric arrangement allows bit lines to intersect pillars at optimized positions, reducing the depth and complexity of required etches while maintaining the three-dimensional vertical channel structure and memory functionality.
Solution Approach 2:
The pillar arrangement utilizes lateral shifting between alternating rows to create an optimized geometric configuration. This dimensional adjustment in the lateral plane enables reduced etch depths by positioning pillars where bit lines can access them more efficiently, thereby simplifying the vertical etching process while preserving the 3D memory architecture.
Data Source
AI summary
Roughly described, a memory device has a multilevel stack of conductive layers. Pillars oriented orthogonally to the substrate each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines (SSLs) are disposed above the conductive layers, and bit lines are disposed above the SSLs. The pillars are arranged on a regular grid having a unit cell which is a non-rectangular parallelogram. The pillars may be arranged so as to define a number of parallel pillar lines, each having an acute angle θ>0° relative to the bit line conductors, each line of pillars having n>1 pillars intersecting a common one of the SSL. The arrangement permits higher bit line density, a higher data rate due to increased parallelism, and a smaller number of SSLs, thereby reducing disturbance, reducing power consumption and reducing unit cell capacitance.