Parallelogram Contact Plug Layout for DRAM Isolation
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Solution Overview
Problem
In DRAM devices, the miniaturization of memory cells leads to short circuits between storage node contact plugs and bit line contact plugs due to overlapping active regions, causing process and product issues, and making it difficult to maintain sufficient capacitance and signal-to-noise ratio.
Innovation Solution
A method for forming contact plug layouts where active region patterns overlap buried gate patterns to create contact plug regions, with contact plug patterns being reshaped into parallelograms or rhombus shapes that partially overlap the buried gate patterns, ensuring larger contact openings and electrical isolation by exposure of isolation structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are miniaturized to increase integration density, then productivity and integration density improve, but short circuits occur between storage node contact plugs and bit line contact plugs due to overlapping active regions
Solution Approach 1:
The patent applies asymmetry by changing the contact plug pattern from a symmetric rectangular shape to an asymmetric shape where the pattern is shifted relative to the active region. This asymmetric positioning ensures that the contact plug opens do not overlap with the active region, thereby preventing short circuits between storage node contact plugs and bit line contact plugs while maintaining high integration density
Solution Approach 2:
The patent addresses the two-dimensional overlapping problem by introducing a dimensional shift in the contact plug pattern positioning. Instead of simply reducing size, the solution shifts the contact plug pattern in a specific direction relative to the active region, effectively using positional dimensionality to prevent overlap and ensure electrical isolation
2Ease of manufacture
If contact plug patterns are formed directly over active regions, then manufacturing simplicity is maintained, but short circuits occur between bit line contact plugs and storage node contact plugs
Solution Approach 1:
The patent applies preliminary action by pre-shifting the contact plug pattern during the photolithography step before opening formation. This preliminary positional adjustment ensures that when the contact plug opens are formed, they are already positioned to avoid overlapping with the active region, preventing short circuits while maintaining a relatively simple manufacturing process
Solution Approach 2:
The patent replaces complex mechanical alignment and positioning systems with a photolithographic pattern design approach. By encoding the positional offset directly into the photomask pattern, the system eliminates the need for complex mechanical alignment mechanisms while achieving reliable electrical isolation
3Productivity
If active region area is reduced to maintain cell area, then integration density improves, but capacitance and signal-to-noise ratio decrease
Solution Approach 1:
The patent addresses the capacitance limitation by extending the capacitor structure vertically into the third dimension. The stacked capacitor configuration allows the capacitor to extend upward from the substrate, providing sufficient capacitance value even when the planar active region area is reduced, thereby maintaining signal-to-noise ratio while improving integration density
Data Source
AI summary
A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.