Parallelogram Transistor Layout for SRAM Misalignment Tolerance
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Solution Overview
Problem
The challenge in semiconductor integrated circuit processing is maintaining balance between high packing density and yield, particularly due to misalignment and crystal orientation variations in SRAM cells, leading to asymmetry and significant performance deviations in memory cell parameters like static noise margin and trip voltage.
Innovation Solution
The design of a symmetrical circuit with P-channel transistors featuring channels in the shape of parallelograms with acute angles, ensuring equal effective widths and alignment with polycrystalline silicon gates, regardless of crystal orientation, to maintain balance and reduce misalignment-induced imbalances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional rectangular transistor channels are used in SRAM cells, then manufacturing process is simple, but misalignment and crystal orientation variations cause asymmetry and significant performance deviations
Solution Approach 1:
The patent applies asymmetry by designing the transistor channel in a parallelogram shape with acute angles instead of conventional rectangular symmetry. This asymmetric geometry compensates for misalignment effects by ensuring that the effective channel width remains equal for both transistors in the SRAM cell even when fabrication misalignment occurs, thereby improving performance consistency without requiring higher manufacturing precision.
2Area of moving object
If transistor feature sizes are shrunk to increase packing density, then area efficiency improves, but second order effects and misalignment sensitivity increase
Solution Approach 1:
The patent changes the geometric parameters of the transistor channel from rectangular to parallelogram shape with specific acute angles. This parameter change allows the effective channel width to be insensitive to misalignment variations, enabling smaller feature sizes to be used while maintaining manufacturing tolerance and reducing the impact of second order effects on performance.
3Device complexity
If symmetrical rectangular transistor layouts are used, then design simplicity is maintained, but performance varies significantly due to crystal orientation and misalignment
Solution Approach 1:
The patent replaces symmetrical rectangular layouts with asymmetric parallelogram-shaped channels oriented at acute angles. This asymmetric design maintains relative simplicity while significantly improving reliability by making the effective channel width equal for both transistors despite crystal orientation variations and fabrication misalignment, thereby consistent static noise margin and performance.
Data Source
AI summary
A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.