Parameterized Cell Manipulation in Custom Layout Design

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Solution Overview

Problem

IC designers face challenges in efficiently manipulating parameterized cells within EDA tools to achieve optimal circuit density and avoid design rule violations, leading to performance issues and errors in custom layout designs.

Innovation Solution

A system and method for manipulating parameterized cells by adjusting configurable attributes such as parameter mapping, port mapping, abutment, directional extension, and boundary layer capabilities, allowing for dynamic configuration and layout adjustments within EDA tools, utilizing a processor, display, and input device to generate new configurations for improved custom layout designs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If manual and automated layout tools are used to maximize circuit density, then circuit density is improved, but design complexity and error introduction increase

Engineering Contradiction:
Improvecircuit densityVSAvoidlayout manipulation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The system enables dynamic adjustment of configurable attributes (such as channel width, finger number, extension dimensions) of parameterized cells through parameter mapping capabilities. This allows designers to modify cell parameters directly without manual layout manipulation, thereby maintaining circuit density while reducing layout complexity and potential errors.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention uses parameterized cell instances that can be copied and configured with different parameters. Instead of manually manipulating each cell layout, designers work with parameter definitions that automatically generate and update the corresponding layout instances, reducing manual effort and errors while maintaining optimal density.

Inventive Principle:
Principle #26Copying

2Productivity

If parameterized cells are used to accelerate layout tasks, then productivity is improved, but ease of operation and control are reduced

Engineering Contradiction:
Improvelayout task accelerationVSAvoidparameter manipulation ease
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The system introduces an intermediary layer of parameter mapping capabilities that bridge the gap between high-level parameter definitions and detailed layout configurations. This intermediary interface simplifies operation by allowing designers to control parameterized cells through intuitive parameter adjustments rather than complex layout manipulations, thereby maintaining ease of operation while preserving productivity benefits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If complex shapes and devices are generated and edited within EDA tools, then design flexibility is improved, but design rule verification errors increase

Engineering Contradiction:
Improvedesign flexibilityVSAvoiddesign rule verification accuracy
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system maintains design flexibility by allowing configuration of various cell parameters (channel width, length, number of fingers, extensions) while ensuring design rule compliance through automated parameter mapping. The parameter mapping capability automatically adjusts parameters to meet design rules, thereby maintaining flexibility while improving verification accuracy and reducing errors.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9852251B2Manipulating parameterized cell devices in a custom layout design
Publication Date: 2017.12.26 SYNOPSYS INC
  • US9852251B2 patent drawing
  • US9852251B2 patent drawing
  • US9852251B2 patent drawing

AI summary

A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.