Parameterized Digital Divider for Programmable Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital division techniques require substantial logic resources and circuitry, leading to increased complexity, size limitations, and slow performance in programmable logic devices due to serpentine data paths and resource constraints.
Innovation Solution
A method and system for digital division that involves right-shifting the divider to create a temporary divider, determining a temporary dividend, subtracting the temporary divider from the temporary dividend to find a difference, and left-shifting the quotient based on this difference, utilizing a digital divider with integrated right-shift, subtraction, and left-shift circuits, along with a counter and division circuit for configurable bit-width operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional digital division techniques are implemented in programmable logic devices, then digital division functionality is achieved, but substantial logic resources and circuitry are required, limiting data word size and precision
Solution Approach 1:
The division operation is segmented into multiple clock cycles, with each cycle processing a portion of the division. The divider is right-shifted and compared with the dividend in iterative steps, allowing the division to be completed through multiple smaller operations rather than requiring all logic resources simultaneously. This enables larger data word sizes without proportionally increasing logic resource requirements.
Solution Approach 2:
The digital divider implementation is made dynamic and configurable through parameterized design. The divider can be configured for different data widths and precision requirements, allowing the same hardware structure to adapt to various data word sizes. This dynamic configurability resolves the contradiction by enabling versatile data processing without requiring dedicated hardware for each specific division size.
2Productivity
If serpentine data paths are used to connect logic circuitry within an integrated circuit, then digital division is performed, but delay increases and performance becomes slow
Solution Approach 1:
The division operation is divided into multiple clock cycles, with each cycle performing a specific sub-operation (right-shift, comparison, subtraction, left-shift). This temporal segmentation allows data to flow through shorter, more direct paths in each cycle rather than requiring long serpentine paths to connect all logic elements sequentially, thereby reducing overall delay and improving performance.
Solution Approach 2:
The divider is right-shifted in advance at the beginning of each clock cycle before the comparison and subtraction operations. This preliminary action prepares the data in a form that enables faster subsequent operations, reducing the overall time required for the division operation and improving productivity without requiring extended data paths.
3Reliability
If large amounts of logic resources are allocated for digital division, then division functionality is achieved, but the size of the integrated circuit increases and cost increases
Solution Approach 1:
The digital divider is designed with universal, parameterized logic circuits that can perform division operations for different data widths and precision requirements. The same core logic resources are reused across multiple division operations and configurations, ensuring reliable division functionality while minimizing the integrated circuit area required. The parameterized design allows a single hardware implementation to serve multiple division scenarios.
Solution Approach 2:
The divider implementation uses parameterized design where the logic resources are configured based on the required data width and precision. By changing parameters such as the number of bits for the dividend and divisor, the same hardware structure can adapt to different division requirements without requiring additional logic resources, thereby maintaining reliability while reducing circuit area.
Data Source
AI summary
A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The counter provides a count, and the division circuit is operatively coupled to the counter. The division circuit divides a dividend by a divider to provide a quotient in response to the counter. At least one of the counter and division circuit is configured to accept at least one of the count, dividend, divider, and quotient with a configurable bit-width.