Parameterized Interface Protection for Electronic Design Validation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IC design verification methods face challenges in ensuring compatibility and functionality between components, particularly when using intellectual property blocks from external vendors, leading to increased design time and potential engineering errors, and require a system to verify connectivity and communication.
Innovation Solution
A system and method that modifies electronic designs to add hardware validation by adding or modifying components, signals, and re-routing to ensure components are functioning and communicating, using interface protection parameters and redundancy schemes like parity and ECC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual verification code is written for each interface type, then verification coverage is improved, but development time and complexity increase
Solution Approach 1:
The patent creates a universal verification framework that can handle multiple interface types (AXI, APB, PCI, etc.) through a single unified approach. The verification system uses a common set of primitives and methodologies that can be applied across different interface types, eliminating the need to write separate verification code for each interface type while maintaining comprehensive verification coverage.
Solution Approach 2:
The patent employs template-based verification code generation where verified interface types serve as templates that can be copied and instantiated for other interface types. This allows the verification logic to be reused across different interfaces, reducing development time and complexity while maintaining thorough verification coverage through systematic instantiation of verified patterns.
2Ease of operation
If software-based verification is used, then ease of implementation is improved, but processor loading and response time worsen
Solution Approach 1:
The patent replaces software-based verification mechanisms with hardware-based verification primitives that operate at the circuit level. Instead of using processor-executed verification code, the system employs dedicated verification hardware blocks that can detect interface violations independently of the main processor, thereby reducing processor loading while maintaining verification functionality.
Solution Approach 2:
The patent introduces intermediary verification hardware components that act as mediators between the interface signals and the verification logic. These intermediary blocks receive interface signals and generate verification results independently of the main processor, allowing verification to occur in parallel without consuming processor resources or increasing response time.
3Speed
If hardware verification is implemented, then response time is improved, but compatibility between components worsens
Solution Approach 1:
The patent employs configurable verification parameters that can be adjusted to match different interface types and component specifications. The verification system allows parameter changes in protection strength, verification depth, and monitoring granularity to be optimized for each specific interface type, enabling fast hardware verification response times while maintaining compatibility with various component standards through adaptive parameter configuration.
Solution Approach 2:
The patent divides the verification system into separate, modular verification primitives that can be independently configured and applied to different interface segments. This segmentation allows the verification functionality to be tailored to specific interface types without affecting other parts of the system, thereby maintaining compatibility across different components while achieving fast verification response times through parallel processing of multiple interface segments.
4Reliability
If interface protection parameters are added, then communication security is improved, but device complexity increases
Solution Approach 1:
The patent implements nested verification structures where protection parameters are organized in hierarchical layers. The verification system embeds multiple levels of protection mechanisms within each other, allowing different protection strengths to be nested according to the security requirements of each interface type. This nesting approach enables enhanced communication security while managing device complexity through structured organization of verification functions.
Solution Approach 2:
The patent applies partial verification protection to different interface segments based on their security requirements. Instead of applying maximum protection uniformly across all interfaces, the system selectively applies appropriate protection levels to each interface type, using partial action where sufficient protection is achieved with lower complexity and excessive action only where absolutely necessary, thereby balancing communication security with device complexity.
Data Source
AI summary
A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.