Parameterized Interleaver Layout for Low-Memory Error Control

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Solution Overview

Problem

Existing interleaver designs, such as S-random interleavers, lack a general rule to specify interleavers of any size, requiring explicit listing and significant memory storage, making them impractical for communication systems with varying interleaver lengths.

Innovation Solution

A parameterized interleaver design process that optimizes interleaver design for any size using a few design parameters, reducing memory requirements and improving performance to match or exceed that of S-random interleavers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If explicit listing of entire interleaver is used to specify interleaver of size N, then interleaver performance is maintained, but memory storage requirement increases significantly

Engineering Contradiction:
Improveinterleaver performanceVSAvoidmemory storage requirement
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent transforms the interleaver specification from explicit listing of all N elements to a compact parameterized form using only 6 parameters (s, p, N1, K1, K2, K3). This parameterization approach maintains the interleaver's error floor prevention performance while reducing memory storage from O(N) to O(1), resolving the contradiction between performance and storage requirements.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of storing the entire interleaver sequence, the patent stores a compact parameter set that can generate the interleaver on-demand. The parameterized form acts as a compressed representation that reproduces the full interleaver sequence only when needed for actual interleaving operations, significantly reducing memory footprint.

Inventive Principle:
Principle #26Copying

2Reliability

If S-random interleaver is used to prevent early error floors, then error rate performance improves, but device complexity increases due to lack of general rule

Engineering Contradiction:
Improveerror rate performanceVSAvoidinterleaver design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a general parametric form with 6 parameters that can specify any S-random interleaver of any size N. This parameterization provides a unified design rule that simplifies the design process while maintaining the error floor prevention capability, resolving the contradiction between performance and design complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The parameterized interleaver design creates a universal framework that can generate interleavers of any size N by adjusting the parameters. This single general rule replaces the need for separate design approaches for different interleaver sizes, reducing design complexity while maintaining performance across various system requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If interleaver size is increased to improve error rate performance, then reliability improves, but memory storage requirement increases

Engineering Contradiction:
Improveerror rate performanceVSAvoidmemory storage requirement
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent enables scalable interleaver design where performance can be improved by adjusting parameters (such as increasing N1 or changing the permutation patterns) without proportionally increasing memory storage. The parameterized form keeps storage constant at O(1) while allowing flexible adjustment of interleaver size and complexity to meet performance requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP2429084B1Method and apparatus for a parameterized interleaver design process
Publication Date: 2013.12.25 HUGHES NETWORK SYST
  • EP2429084B1 patent drawingFigure 1A
  • EP2429084B1 patent drawingFigure 1B
  • EP2429084B1 patent drawingFigure 2

AI summary

A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.