Parameterized SoC Architecture for Multi-Version Chip Design
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Solution Overview
Problem
The challenge of designing multiple system-on-a-chip (SOC) configurations for diverse applications with varying performance levels without incurring excessive development costs and avoiding performance degradation or inefficiencies, such as power consumption and signal degradation, is addressed by using an integrated design process to create a family of SOCs sharing a common architecture with parameterized design information.
Innovation Solution
A family of SOCs is developed using an integrated design process where a common architecture is defined by a collection of design information, allowing different configurations through parameterized components, enabling efficient design and verification of multiple SOCs with shared testing and validation, and configuration circuitry for selective component disabling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple SOCs are designed separately for different applications, then each SOC can be optimized for its specific application, but development costs and time increase significantly
Solution Approach 1:
The patent implements a universal SOC architecture that can serve multiple applications through parameterized design. The common architecture includes configurable components such as processor cores, memory controllers, and I/O interfaces that can be customized via parameters to meet different application requirements, thereby achieving both application-specific optimization and efficient reuse across multiple products
Solution Approach 2:
The patent employs parameterized design information where architectural parameters (such as number of processor cores, memory size, I/O configurations) can be varied to generate different SOC versions from the same base architecture. This allows rapid adaptation to different applications without redesigning the entire SOC, thus improving both versatility and development efficiency
2Reliability
If a high-performance SOC configuration is used for all applications, then maximum performance is achieved, but power consumption and cost increase for applications that do not require full performance
Solution Approach 1:
The patent applies local quality by enabling selective activation of SOC components based on application needs. Configuration circuitry allows specific modules (such as GPU, NPU, or high-speed I/O) to be enabled or disabled, ensuring that only the necessary performance-critical components consume power, thus reducing overall power consumption while maintaining required performance levels
Solution Approach 2:
The patent implements dynamic configurability where the SOC can adapt its component activation state based on operational requirements. Configuration circuitry and control logic enable the system to dynamically adjust which components are active, transitioning between high-performance and low-power states as needed, thereby optimizing the balance between performance and power consumption
3Use of energy by moving object
If configuration circuitry is added to enable selective component disabling, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the SOC into independently controllable functional modules, each with its own configuration controls. This modular approach allows configuration circuitry to be distributed and localized to specific components rather than requiring a complex centralized control system, thereby reducing overall device complexity while maintaining the ability to selectively disable components for power savings
Data Source
AI summary
A family of systems-on-a-chip (SOCs) produced using an integrated design methodology is disclosed. The methodology includes defining representations of a plurality of components for a first SOC in a collection of design information, where at least a first component of the plurality of components is modified for inclusion in a second SOC that includes at least a subset of the plurality of components. At least a portion of the collection of design information is parameterized to reflect the first component in the first SOC and the modified first component in the second SOC. Netlists for the first and second SOC are produced from the plurality of source code files using respective first and second sets of parameters.