On-Chip Parametric Monitors for IC Reliability Warning

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Solution Overview

Problem

Conventional methods for evaluating the reliability of integrated circuits and providing early warnings for potential failures are inadequate, as they rely on extensive empirical validation and do not effectively measure parametric variations or account for layout environments, leading to limited ability to predict and prevent system failures.

Innovation Solution

A method utilizing on-chip parametric monitors to identify key parameters, insert parametric macros, and monitor semiconductor products under stress to issue warnings before device failure, allowing for the separation of parametric and defect contributions to failures, and assessing layout-dependent variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional reliability assessment techniques are used with extensive measurement and stress of many different circuits, then empirical validation of fail rate and reliability prediction is improved, but the complexity of testing and measurement increases significantly

Engineering Contradiction:

Improvereliability prediction accuracyVSAvoidtesting complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential reliability monitoring function from complex conventional testing by implementing dedicated parametric monitor circuits that continuously track threshold voltage shifts. This extraction allows reliability assessment without requiring extensive stress testing of multiple circuits, reducing testing complexity while maintaining prediction accuracy.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces parametric monitor circuits as intermediary elements that indirectly measure reliability parameters (threshold voltage shifts) without requiring direct stress testing of functional circuits. These monitors act as mediators between the stressed circuits and the reliability assessment system, simplifying the overall testing process.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If conventional measurement structures are used that are not cycled during stress, then measurement simplicity is maintained, but the representativeness of measured parametric variation deteriorates

Engineering Contradiction:

Improvemeasurement simplicityVSAvoidparametric variation measurement accuracy

Core Design Contradiction:

Ease of operationVSMeasurement precision

Solution Approach 1:

The patent implements parametric monitor circuits that are pre-configured and cycled during stress periods before actual reliability testing begins. This preliminary action ensures that the monitors are properly activated and tracking parametric variations from the start of stress, improving measurement accuracy without complicating the overall process.

Inventive Principle:

Principle #10Preliminary action

3Area of stationary object

If no on-chip parametric monitors are implemented, then chip area and manufacturing cost are reduced, but the ability to detect and warn of potential failures is lost

Engineering Contradiction:

Improvechip areaVSAvoidfailure detection capability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent designs parametric monitor circuits that serve multiple functions: they continuously track threshold voltage shifts, provide early warning of potential failures, and enable reliability assessment without requiring separate dedicated testing infrastructure. This multi-functionality justifies the additional chip area by consolidating multiple reliability functions into single monitor structures.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Device complexity

If conventional techniques that do not separate parametric and defect contributions are used, then measurement process is simplified, but the ability to identify specific failure mechanisms deteriorates

Engineering Contradiction:

Improvemeasurement process complexityVSAvoidfailure mechanism identification

Core Design Contradiction:

Device complexityVSLoss of information

Solution Approach 1:

The patent segments the reliability assessment into distinct components by implementing separate parametric monitor circuits that specifically track threshold voltage shifts (parametric variations) independent of defect-induced failures. This segmentation allows clear differentiation between parametric degradation and defect contributions, providing detailed failure mechanism identification without excessive complexity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8949767B2Reliability evaluation and system fail warning methods using on chip parametric monitors

Publication Date: 2015.02.03 SIEMENS INDUSTRY SOFTWARE INC

AI summary

A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.