Parametric Yield Analysis for Transistor Design Optimization
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in accurately estimating and managing parametric yield during chip design and manufacturing, particularly due to the complex interplay of design parameters affecting transistor performance, leading to unpredictable yields and financial uncertainties for manufacturing facilities.
Innovation Solution
A system and method that score the impact of physical design choices on transistor performance, incorporating parameters such as dimensions, across-chip-length-variation, and corner rounding stress effects, to predict and optimize parametric yield by calculating threshold voltage adders and current deviations, enabling comparison with observed data to pinpoint anomalies and improve chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical design choices are made to improve transistor performance, then device performance is improved, but parametric yield becomes more unpredictable and difficult to manage
Solution Approach 1:
The patent segments the complex design parameter space into distinct categories (geometric parameters, material parameters, process parameters) and evaluates their individual and combined effects on transistor performance. This segmentation allows systematic analysis of how different design choices impact both performance and yield, making the complex interplay manageable through structured evaluation frameworks.
2Measurement precision
If comprehensive design parameter analysis is performed to improve parametric yield estimation, then yield prediction accuracy is improved, but analysis time and computational resources increase
Solution Approach 1:
The patent performs preliminary analysis of design parameters during the chip design phase, before manufacturing. By evaluating the potential impact of design choices on parametric yield in advance, the system identifies high-risk design configurations early, allowing designers to make adjustments before committing to fabrication. This preliminary action reduces the need for extensive post-manufacturing analysis and accelerates the overall development cycle.
3Reliability
If design specifications are made more stringent to improve chip performance, then performance specification is improved, but parametric yield loss increases
Solution Approach 1:
The patent systematically evaluates how changes in design parameters affect both performance specifications and parametric yield. By analyzing the sensitivity of transistor performance to parameter variations, the system identifies optimal parameter ranges that satisfy performance requirements while minimizing yield loss. This involves adjusting parameters such as transistor dimensions, material compositions, and process conditions to achieve the best trade-off between performance and yield.
Data Source
AI summary
Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.