Parasitic-Aware Blockage for Capacitance Extraction
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Solution Overview
Problem
Existing methods for generating blockage patterns in parasitic capacitance extraction are sub-optimal in terms of speed and accuracy, failing to explicitly consider electrical characteristics and capture electrical information, leading to a lack of mechanism to optimize the speed versus accuracy trade-off.
Innovation Solution
A parasitic-aware blockage structure is introduced, comprising expanded and merged polygons with associated physical and electrical information, such as capacitance and resistance errors, to facilitate accurate and efficient parasitic capacitance extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed layout patterns are used for blockage representation, then parasitic capacitance extraction accuracy is improved, but extraction speed deteriorates
Solution Approach 1:
The detailed layout is segmented into multiple tiles, where each tile is processed independently to compute blockage patterns. This segmentation allows parallel processing of different regions, improving extraction speed while maintaining accuracy by preserving local geometric details in each tile.
Solution Approach 2:
The patent creates simplified copies of detailed blockage patterns by computing equivalent blockage representations that capture essential electrical characteristics without replicating every geometric detail. These copied blockage patterns are used for parasitic extraction, achieving speed improvement while maintaining sufficient accuracy through error correction mechanisms.
2Productivity
If simple blockage geometries are used, then extraction speed is improved, but parasitic capacitance extraction accuracy deteriorates
Solution Approach 1:
The patent modifies blockage pattern parameters by computing density-dependent parameters and error correction factors that adjust the simplified blockage geometries to better represent the electrical characteristics of detailed layouts. This allows simple geometries to achieve higher accuracy through parameter optimization.
Solution Approach 2:
The patent implements a feedback mechanism where parasitic extraction results are compared against reference values, and error information is used to iteratively refine blockage patterns. This feedback loop enables continuous improvement of accuracy while maintaining computational efficiency.
3Loss of information
If detailed blockage patterns are used, then electrical information accuracy is improved, but processing complexity increases
Solution Approach 1:
The patent extracts only the essential electrical information from detailed blockage patterns by computing equivalent blockage representations that capture key electrical characteristics (such as capacitance and resistance effects) while discarding redundant geometric details. This extraction process reduces complexity while preserving necessary electrical information.
Data Source
AI summary
A parasitic-aware blockage structure is provided to replace a detailed blockage structure for use in connection with a capacitance extraction operation. The parasitic-aware blockage structure includes one or more parasitic-aware blockage polygons, each representing a plurality of polygons of the detailed blockage structure. The parasitic-aware blockage polygons can be formed by expanding and merging the polygons of the detailed blockage structure. Physical information is associated with each of the parasitic-aware blockage polygons, wherein the physical information defines physical characteristics of the polygons of the detailed blockage structure. Capacitance error information may also be associated with each of the parasitic-aware blockage polygons, specifying capacitive errors of the parasitic-aware blockage polygons with respect to the polygons of the detailed blockage structure.