Parasitic Capacitance Database Reuse for IC Layout
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Solution Overview
Problem
The increasing miniaturization of integrated circuits (ICs) has made them more susceptible to parasitic capacitance effects, requiring more accurate and efficient modeling of parasitic capacitance to design smaller and more effective ICs, but existing methods become computationally expensive and slower as the number of cells in layout diagrams increases.
Innovation Solution
A method is disclosed for efficiently determining parasitic capacitance descriptions by selecting a candidate cell, searching a database for a matching predefined cell, and assigning its parasitic capacitance description, with the option to use a 3D field solver if no match is found, and appending the database with new cell data for future reuse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional parasitic capacitance calculation methods are used for each cell individually, then measurement precision is improved, but productivity deteriorates due to repetitive calculations
Solution Approach 1:
The patent creates a database of pre-calculated parasitic capacitance values for representative cells. When processing layout diagrams, instead of calculating parasitic capacitance for every cell individually, the system copies previously calculated values from the database for matching cell types, thereby eliminating repetitive calculations while maintaining accuracy.
Solution Approach 2:
The system performs parasitic capacitance calculations in advance for a set of representative cells and stores these results in a database before actual layout processing. This preliminary action allows subsequent layouts to reuse these pre-computed values, significantly improving processing efficiency without sacrificing measurement precision.
2Productivity
If the database is searched for matching predefined cells, then productivity is improved by avoiding repetitive calculations, but device complexity increases due to database management
Solution Approach 1:
The patent implements a universal database structure that can store and retrieve parasitic capacitance data for multiple cell types and configurations. This single database serves all layout processing needs, providing a multi-functional solution that improves productivity without requiring separate management systems for different cell types.
Data Source
AI summary
A method (of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells) comprises generating the layout diagram including: reusing one amongst predefined parasitic capacitance (PC) descriptions of corresponding predefined cells that are stored within a database, the reusing including: for a candidate cell amongst the layout cells in the layout diagram, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and when a substantial match is found, reusing the PC description of the matching predefined cell by assigning the same to the candidate cell rather than otherwise making a discrete calculation of a corresponding PC description for the candidate cell.