Parasitic Capacitance Estimation in IC Layout Design
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Solution Overview
Problem
As the complexity of integrated circuit designs increases in nanometer technology, verification procedures become time-consuming due to the need for accurate estimation and consideration of parasitic effects, which can degrade circuit performance and require extensive iteration and simulation.
Innovation Solution
The implementation of a near-real-time RC module that estimates parasitic capacitances using back-end-of-line interconnect models and technology files, allowing for earlier and more accurate parasitic-aware design, enabling faster design convergence by inserting lumped capacitor representations into pre-layout simulations and reducing the need for extensive post-layout simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional RC extraction and post-layout simulation are performed to accurately account for parasitic effects, then circuit performance accuracy is improved, but design time and iteration cycles increase significantly
Solution Approach 1:
The patent applies preliminary action by performing parasitic capacitance estimation using the RC module before layout verification and post-layout simulation. The RC module computes estimated parasitic capacitances based on routing path geometry and interconnect models in advance, allowing designers to account for parasitic effects during pre-layout design iterations without waiting for time-consuming post-layout RC extraction and simulation
Solution Approach 2:
The patent uses copying by creating a simplified model of parasitic capacitance through the RC module that replicates the essential electrical characteristics of the actual layout. The module generates estimated capacitance values that copy the behavior of full RC extraction results, enabling accurate performance prediction without requiring the complete post-layout simulation process
2Manufacturing precision
If designers perform multiple iterations of layout modification and post-layout simulation to meet performance specifications, then design accuracy is improved, but productivity decreases due to repeated verification cycles
Solution Approach 1:
The RC module performs preliminary parasitic capacitance estimation before layout finalization, allowing designers to predict performance issues and make corrections during the layout design phase. This preliminary assessment reduces the need for multiple post-layout simulation iterations by identifying and resolving parasitic-related performance problems earlier in the design process
Solution Approach 2:
The system implements feedback by using the RC module to provide rapid parasitic capacitance estimates that inform design decisions during layout creation. The estimated values feed back into the design process, allowing real-time adjustments to routing paths and layout configurations to meet performance specifications before committing to final layout
Data Source
AI summary
A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.