Parasitic Capacitance Prediction in IC Schematic Simulations
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Solution Overview
Problem
The divergence between pre-layout and post-layout simulation results for integrated circuits due to parasitic effects makes it difficult to predict circuit performance accurately during early design stages, leading to costly and time-consuming re-optimization processes.
Innovation Solution
A computer-implemented method to determine parasitic capacitance for transistors in integrated circuits using expressions derived from two-dimensional and three-dimensional transistor structures, allowing for accurate estimation of parasitic capacitance before layout, thereby reducing the need for re-design after layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If schematic simulation is performed before layout, then circuit design can be optimized early, but parasitic capacitance effects cause significant divergence from post-layout results (20-50% performance loss)
Solution Approach 1:
The patent applies preliminary action by calculating parasitic capacitance values during the schematic design stage using extracted geometric information from the schematic symbols. This allows accurate performance prediction to be performed early in the design process, before layout is completed, enabling designers to optimize circuits without waiting for post-layout simulation results.
Solution Approach 2:
The patent uses an intermediary approach by introducing a parasitic capacitance extraction mechanism that bridges the gap between schematic-level design and layout-level reality. The extractor captures geometric information from schematic symbols and computes parasitic capacitance values that mediate between the ideal schematic simulation and the actual post-layout performance, enabling accurate early-stage predictions.
2Reliability
If re-optimization is performed after layout to recover performance loss, then circuit performance can be improved, but design cycle is lengthened and cost increases
Solution Approach 1:
By performing parasitic capacitance extraction and performance evaluation during the schematic design stage, the patent enables preliminary optimization actions to be taken before layout. This eliminates or reduces the need for costly re-optimization iterations after layout, as performance issues can be identified and resolved early when changes are easier and cheaper to implement.
3Measurement precision
If accurate parasitic capacitance modeling is implemented using 3D transistor structures, then prediction accuracy improves, but computational complexity and processing requirements increase
Solution Approach 1:
The patent extracts only the essential geometric information needed for parasitic capacitance calculation from the schematic symbols, rather than requiring full 3D layout data. This extraction approach maintains high prediction accuracy while significantly reducing the complexity and computational burden compared to complete 3D modeling approaches.
Solution Approach 2:
The patent changes the modeling parameters by using simplified geometric representations extracted from schematic symbols rather than full 3D structural data. This parameter simplification maintains the essential physics for accurate parasitic capacitance prediction while dramatically reducing computational complexity and data requirements.
Data Source
AI summary
A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (320). The first set of coefficients can be inserted into the first expression (325). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (345). The second expression can include the first expression (350). The method can include inserting the second set of coefficients into the second expression and outputting the second expression (355).